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1.发明授权Circuits and methods for power management in a processor-based system and systems using the same 有权基于处理器的系统中的电源管理的电路和方法以及使用该系统的系统公开(公告)号：US07000138B1
公开(公告)日：2006-02-14
申请号：US09876299
申请日：2001-06-07
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： An adaptive clock throttle 600 interfacing a clock generator 601 generating a high speed clock and a processing engine 602 operating in response to a processing clock. Adaptive clock throttle 600 generates a plurality of lower speed clocks from the high speed clock, estimates a duty cycle of the processing engine, and selectively gates one of the lower speed clocks to the processing engine as the processing clock to increase the duty cycle of the processing engine.
摘要翻译： 自适应时钟节流阀600，其连接产生高速时钟的时钟发生器601和响应于处理时钟操作的处理引擎602。 自适应时钟节流阀600从高速时钟产生多个较低速时钟，估计处理引擎的占空比，并且选择性地将处理引擎中的一个低速时钟作为处理时钟，以增加处理引擎的占空比 处理引擎。
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2.发明授权Circuits and methods for extracting a clock from a biphase encoded bit stream and systems using the same 有权用于从双相编码位流中提取时钟的电路和方法以及使用该时钟的系统公开(公告)号：US06782300B2
公开(公告)日：2004-08-24
申请号：US09730284
申请日：2000-12-05
IPC分类号： G06F1700
CPC分类号： H04L25/4904 , H04H20/95 , H04L7/0331 , H04L7/04
摘要： A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.
摘要翻译： 从双相编码比特流中提取时钟的方法包括检测每个具有在连续比特相位转换之间测量的样本大小的样本流的步骤。 对于每个样本确定样本长度，样本长度近似相应样本大小中最小公倍数。 从样本序列的样本长度检测前导码并被解码以确定在预期时钟边沿的转变之后的时钟的预期逻辑电平。 时钟的预期电平通过双相编码数据门控，以在时间窗口的打开之前产生控制信号。 然后控制信号通过双相编码数据进行门控，以在时间窗口打开后提取时钟沿。
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公开(公告)号：US20130082314A1
公开(公告)日：2013-04-04
申请号：US13434511
申请日：2012-03-29
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76838 , H01L21/76843 , H01L23/485 , H01L23/5226 , H01L23/5256 , H01L23/5283 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
摘要翻译： 集成电路在衬底中包含较低的组件，PMD层，PMD层上的上部组件，PMD层中的下部触点将一些上部组件连接到某些较低组件，上部组件上的ILD层，ILD上的金属互连线 层和上部触点，其将一些上部部件连接到某些金属互连线，并且还包括与上部环形触点对准的下部环形触点的环形堆叠触点。 下触点和上接触件都具有衬垫上的金属衬垫和接触金属。 下环形触头具有至少一个衬垫金属环和围绕PMD材料柱的接触金属，并且上触点具有至少一个衬垫金属环和围绕ILD材料柱的接触金属。 环形堆叠的触点将金属互连件连接到下部组件。
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公开(公告)号：US08652855B2
公开(公告)日：2014-02-18
申请号：US13434511
申请日：2012-03-29
IPC分类号： H01L21/00 , H01L21/8242 , H01L21/02 , H01L21/108 , H01L23/48
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76838 , H01L21/76843 , H01L23/485 , H01L23/5226 , H01L23/5256 , H01L23/5283 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.
摘要翻译： 集成电路在衬底中包含较低的组件，PMD层，PMD层上的上部组件，PMD层中的下部触点将一些上部组件连接到某些较低组件，上部组件上的ILD层，ILD上的金属互连线 层和上部触点，其将一些上部部件连接到某些金属互连线，并且还包括与上部环形触点对准的下部环形触点的环形堆叠触点。 下触点和上接触件都具有衬垫上的金属衬垫和接触金属。 下环形触头具有至少一个衬垫金属环和围绕PMD材料柱的接触金属，并且上触点具有至少一个衬垫金属环和围绕ILD材料柱的接触金属。 环形堆叠的触点将金属互连件连接到下部组件。
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公开(公告)号：US07391241B2
公开(公告)日：2008-06-24
申请号：US11192969
申请日：2005-07-29
CPC分类号： H03K19/00346
摘要： A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.
摘要翻译： 去交点电路利用耦合到输入信号的第一触发器和耦合到电路的输出的第二触发器，其具有从输出到门的反馈以控制到第一触发器的第一和第二输入。 在替代方案中，在第一触发器的输出和第二触发器的输入之间提供一个计数器，以提供灵活性以及延迟延迟的可能性。
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公开(公告)号：US20060103432A1
公开(公告)日：2006-05-18
申请号：US11192969
申请日：2005-07-29
IPC分类号： G01R29/02
CPC分类号： H03K19/00346
摘要： A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.
摘要翻译： 去交点电路利用耦合到输入信号的第一触发器和耦合到电路的输出的第二触发器，其具有从输出到门的反馈以控制到第一触发器的第一和第二输入。 在替代方案中，在第一触发器的输出和第二触发器的输入之间提供一个计数器，以提供灵活性以及延迟延迟的可能性。
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