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    Integrated Circuit with Integrated Decoupling Capacitors
    1.
    发明申请
    Integrated Circuit with Integrated Decoupling Capacitors 有权
    集成电路与集成去耦电容

    公开(公告)号：US20130062733A1

    公开(公告)日：2013-03-14

    申请号：US13330833

    申请日：2011-12-20

    Applicant: Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

    Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

    IPC: H01L29/92 ,  H01L21/02

    CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

    Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

    Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

    Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages
    3.
    发明授权
    Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages 有权
    参考发生器系统和使用降低的位线电压读取铁电存储器单元的方法

    公开(公告)号：US06970371B1

    公开(公告)日：2005-11-29

    申请号：US10847412

    申请日：2004-05-17

    Applicant: Scott Robert Summerfelt ,  Hugh P. McAdams

    Inventor： Scott Robert Summerfelt ,  Hugh P. McAdams

    IPC: G11C5/14 ,  G11C11/22

    CPC classification number: G11C11/22 ,  G11C5/147

    Abstract: Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).

    Abstract translation: 提供了方法（200）和系统（108），用于从将铁电信号（PL）施加到目标单元之前从感测放大器输入（SABL / SABLB）去除电荷的铁电存储器单元（106）读取数据 电容器（C FE）。 在感测放大器输入（SABL / SABLB）最初预充电到零伏的情况下，当施加平行线信号（PL）时，提取电荷在数据位线（BL / BLB）上提供负电压，允许施加足够的电压 跨越电池电容器（C SUB FE）以及降低的线路电压（PL）。

    Integrated circuit with integrated decoupling capacitors
    4.
    发明授权
    Integrated circuit with integrated decoupling capacitors 有权
    具集成去耦电容的集成电路

    公开(公告)号：US08753952B2

    公开(公告)日：2014-06-17

    申请号：US13330833

    申请日：2011-12-20

    Applicant: Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

    Inventor： Scott Robert Summerfelt ,  John A. Rodriguez ,  Huang-Chun Wen ,  Steven Craig Bartling

    IPC: H01L21/20

    CPC classification number: H01L27/0805 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L29/92

    Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

    Abstract translation: 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

    Low resistance stacked annular contact
    5.
    发明授权
    Low resistance stacked annular contact 有权
    低电阻堆叠环形接触

    公开(公告)号：US08652855B2

    公开(公告)日：2014-02-18

    申请号：US13434511

    申请日：2012-03-29

    Applicant: Scott Robert Summerfelt ,  Hasibur Rahman ,  John Paul Campbell

    Inventor： Scott Robert Summerfelt ,  Hasibur Rahman ,  John Paul Campbell

    IPC: H01L21/00 ,  H01L21/8242 ,  H01L21/02 ,  H01L21/108 ,  H01L23/48

    CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/5283 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

    Abstract translation: 集成电路在衬底中包含较低的组件，PMD层，PMD层上的上部组件，PMD层中的下部触点将一些上部组件连接到某些较低组件，上部组件上的ILD层，ILD上的金属互连线 层和上部触点，其将一些上部部件连接到某些金属互连线，并且还包括与上部环形触点对准的下部环形触点的环形堆叠触点。 下触点和上接触件都具有衬垫上的金属衬垫和接触金属。 下环形触头具有至少一个衬垫金属环和围绕PMD材料柱的接触金属，并且上触点具有至少一个衬垫金属环和围绕ILD材料柱的接触金属。 环形堆叠的触点将金属互连件连接到下部组件。

    LOW RESISTANCE STACKED ANNULAR CONTACT
    7.
    发明申请
    LOW RESISTANCE STACKED ANNULAR CONTACT 有权
    低电阻堆叠环形接触

    公开(公告)号：US20130082314A1

    公开(公告)日：2013-04-04

    申请号：US13434511

    申请日：2012-03-29

    Applicant: Scott Robert Summerfelt ,  Hasibur Rahman ,  John Paul Campbell

    Inventor： Scott Robert Summerfelt ,  Hasibur Rahman ,  John Paul Campbell

    IPC: H01L23/525 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/5283 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

    Abstract translation: 集成电路在衬底中包含较低的组件，PMD层，PMD层上的上部组件，PMD层中的下部触点将一些上部组件连接到某些较低组件，上部组件上的ILD层，ILD上的金属互连线 层和上部触点，其将一些上部部件连接到某些金属互连线，并且还包括与上部环形触点对准的下部环形触点的环形堆叠触点。 下触点和上接触件都具有衬垫上的金属衬垫和接触金属。 下环形触头具有至少一个衬垫金属环和围绕PMD材料柱的接触金属，并且上触点具有至少一个衬垫金属环和围绕ILD材料柱的接触金属。 环形堆叠的触点将金属互连件连接到下部组件。

    Enhanced storage states in an memory
    9.
    发明授权
    Enhanced storage states in an memory 失效
    内存中增强的存储状态

    公开(公告)号：US06807080B2

    公开(公告)日：2004-10-19

    申请号：US10150744

    申请日：2002-05-17

    Applicant: Jurgen Thomas Rickes ,  Hugh Pryor McAdams ,  Scott Robert Summerfelt

    Inventor： Jurgen Thomas Rickes ,  Hugh Pryor McAdams ,  Scott Robert Summerfelt

    IPC: G11C1122

    CPC classification number: G11C11/22

    Abstract: A memory with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

    Abstract translation: 具有增强存储状态的机制的存储器，而不将电压提升到损坏存储单元结构的电平。 根据本教导的存储单元包括能够切换存储状态的存储结构。 根据本教导的存储器包括通过向存储结构的第一节点施加第一电压并且将第二电压施加到存储结构的第二节点来写入存储单元的装置，使得第一和第二电压具有相反的 极性

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