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1.发明授权Hub interface unit and application unit interfaces for expanded direct memory access processor 有权Hub接口单元和应用单元接口，用于扩展的直接存储器访问处理器公开(公告)号：US06594713B1
公开(公告)日：2003-07-15
申请号：US09637492
申请日：2000-08-11
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： An expanded direct memory access processor has ports which may be divided into two sections. The first is an application specific design referred to as the application unit, or application unit. Between the application unit and the expanded direct memory access processor hub is a second module, known as the hub interface unit hub interface unit which serves several functions. It provides buffering for read and write data, it prioritizes read and write commands from the source and destination pipelines such that the port sees a single interface with both access types consolidated and finally, it acts to decouple the port interface clock domain from the core processor clock domain through synchronization.
摘要翻译： 扩展的直接存储器存取处理器具有可分为两部分的端口。 第一种是被称为应用单元或应用单元的应用特定设计。 在应用单元和扩展的直接存储器访问处理器集线器之间是第二模块，称为集线器接口单元集线器接口单元，其用于多个功能。 它为读取和写入数据提供缓冲，它优先考虑来自源和目标管道的读取和写入命令，使得端口看到具有两个访问类型的单个接口合并，最后，它用于将端口接口时钟域与核心处理器 时钟域通过同步。
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公开(公告)号：US06985982B2
公开(公告)日：2006-01-10
申请号：US10003856
申请日：2001-10-24
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F13/28
摘要： In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.
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3.发明授权Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor 有权配置总线可重配置/可重新编程接口，用于扩展的直接存储器访问处理器公开(公告)号：US06694385B1
公开(公告)日：2004-02-17
申请号：US09638512
申请日：2000-08-11
IPC分类号： G06F300
CPC分类号： G06F13/4256 , G06F13/28
摘要： The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.
摘要翻译： 配置总线互连协议提供了整个数字信号处理器芯片中的存储器映射寄存器的配置接口。 配置总线是一组并行的通信协议，但是用于控制外设而不是数据传输。 虽然扩展的直接存储器访问处理器被大量优化以最大化数据传输，但是为了便于实现和便携性，使得配置总线协议尽可能简单。
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4.发明授权Parallel transfer size calculation and annulment determination in transfer controller with hub and ports 有权具有集线器和端口的传输控制器的并行传输大小计算和废止确定公开(公告)号：US06658503B1
公开(公告)日：2003-12-02
申请号：US09713611
申请日：2000-11-15
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decision capability is employed. This technique facilitates the process of setting up complex transfers without risking brute force inefficient processor cycles. Annulment determination allows detection of cases when a set of data cannot be output immediately and the destination pipeline postpones execution of the write command.
摘要翻译： 描述了最初开发为DSP内的全局存储器映射的各个位置之间的通信集线器的端口和端口的传送控制器。 使用本发明的技术，采用并行大小计算/写入废止决定能力。 这种技术有助于建立复杂传输的过程，而不会产生强力的低效处理器周期。 当一组数据不能立即输出并且目标流水线推迟写入命令的执行时，废止确定允许检测情况。
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5.发明授权Unified memory system architecture including cache and directly addressable static random access memory 有权统一的内存系统架构，包括缓存和直接可寻址的静态随机存取存储器公开(公告)号：US06606686B1
公开(公告)日：2003-08-12
申请号：US09603645
申请日：2000-06-26
申请人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
发明人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0864 , G06F2212/2515 , G06F2212/601
摘要： A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.
摘要翻译： 数据处理装置包括中央处理单元和可配置为高速缓冲存储器和可直接寻址存储器的存储器。 存储器可选择性地配置为高速缓冲存储器和可直接寻址的存储器，通过将选定数量的方式配置为直接可寻址存储器并且将剩余方式配置为高速缓冲存储器。 控制逻辑禁止标签位匹配地址位的指示，并且如果相应的方式被配置为直接可寻址存储器，则高速缓存条目是最近最少用于高速缓存驱逐的指示。 在替代实施例中，通过将等于2M的选定数量的集合（其中M是整数）配置为高速缓冲存储器并将剩余集合配置为直接可寻址存储器，可选地将存储器配置为高速缓存存储器和直接寻址存储器。
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6.发明授权公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译： 描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。 传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。 在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。 使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。
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7.发明授权Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access 有权多层缓存系统与存储器的一致性有选择地配置为高速缓存或直接访问存储器和直接存储器访问公开(公告)号：US06535958B1
公开(公告)日：2003-03-18
申请号：US09603637
申请日：2000-06-26
申请人： Charles L. Fuoco , Sanjive Agarwala , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
发明人： Charles L. Fuoco , Sanjive Agarwala , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
IPC分类号： G06F1300
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0831 , G06F12/0897
摘要： A data processing system having a central processing unit, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit includes a snoop unit generating snoop accesses to the at least one level one cache upon a direct memory access to the directly addressable memory. The snoop unit generates a write snoop access to both level one caches upon a direct memory access write to or a direct memory access read from the directly addressable memory. The level one cache also invalidates a cache entry upon a snoop hit and also writes back a dirty cache entry to the directly addressable memory. A level two memory is selectively configurable as part level two unified cache and part directly addressable memory.
摘要翻译： 具有中央处理单元，至少一个一级缓存，二级统一高速缓存，直接可寻址存储器和直接存储器访问单元的数据处理系统包括：窥探单元，生成窥探访问至少一级一级高速缓存 直接内存访问直接可寻址的内存。 窥探单元在从直接可寻址存储器读取的直接存储器访问写入或直接存储器访问时，产生对一级缓存的写入窥探访问。 一级缓存还会在侦听命中时使缓存条目无效，并将脏缓存条目写回到可直接寻址的存储器。 二级存储器可选择性地配置为部分二级统一缓存和部分直接可寻址存储器。
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公开(公告)号：US06954468B1
公开(公告)日：2005-10-11
申请号：US09713423
申请日：2000-11-15
CPC分类号： G06F15/17
摘要： The transfer controller with hub and ports uses a write allocation counter and algorithm to control data reads from a source port. The write allocation count is the amount of data that can be consumed immediately by the write reservation station of a slow destination port and the channel data router buffers. This is used to throttle fast source port read operations to whole read bursts until space to adsorb the read data is available. This ensures that the source port response queue is not blocked with data that cannot be consumed by the channel data router and the slow destination port. This condition would otherwise block a fast source port from providing data to the other destination ports.
摘要翻译： 具有集线器和端口的传输控制器使用写入分配计数器和算法来控制源端口的数据读取。 写分配计数是缓慢目的地端口的写保留站和信道数据路由器缓冲器可以立即消耗的数据量。 这用于将快速源端口读取操作限制为整个读取脉冲串，直到吸收读取数据的空间可用。 这样可确保源端口响应队列不被通道数据路由器和缓慢目标端口不能使用的数据阻塞。 否则，此条件将阻止快速源端口向其他目标端口提供数据。
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9.发明授权Effective channel priority processing for transfer controller with hub and ports 有权具有集线器和端口的传输控制器的有效信道优先级处理公开(公告)号：US06681270B1
公开(公告)日：2004-01-20
申请号：US09713563
申请日：2000-11-15
IPC分类号： G06F300
CPC分类号： G06F13/387
摘要： A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a first-in-first-out fashion at the data source ports. Each data transfer request has a priority level for execution. In effective channel priority processing the priority level assigned to a source port is the greatest priority level of any data transfer request in the corresponding first-in-first-out queue. This techniques prevents a low priority data transfer request at the output of a source port queue from blocking a higher priority data transfer request further back in the queue. Raising the priority of all data transfer requests within a source port queue enables the low priority data transfer request to complete enabling the high priority data transfer request to be reached. Thus both the low priority data transfer request and the high priority data transfer request in the queue of a single port are serviced before intermediate priority data transfer requests at the output of other source port queues.
摘要翻译： 具有集线器和端口的数据传输控制器使用有效的信道优先级处理技术和算法。 数据传输请求在数据源端口以先进先出的方式排队。 每个数据传输请求具有执行的优先级。 在有效的信道优先级处理中，分配给源端口的优先级是相应的先进先出队列中任何数据传输请求的最高优先级。 该技术防止在源端口队列的输出端的低优先级数据传输请求阻塞更高优先级的数据传输请求进一步返回到队列中。 提高源端口队列内所有数据传输请求的优先级使得能够实现低优先级数据传输请求，从而能够实现高优先级的数据传输请求。 因此，在其他源端口队列的输出处的中间优先级数据传输请求之前，对单个端口的队列中的低优先级数据传输请求和高优先级数据传输请求进行服务。
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公开(公告)号：US06868087B1
公开(公告)日：2005-03-15
申请号：US09713609
申请日：2000-11-15
申请人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
发明人： Sanjive Agarwala , Iain Robertson , David A. Comisky , Charles L. Fuoco , Christopher L. Mobley
CPC分类号： H04L47/6215 , H04L47/50
摘要： A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.
摘要翻译： 具有集线器和端口的传输控制器被视为全局存储器映射的各个位置之间的通信集线器。 请求队列管理器作为传输控制器的关键部分。 请求队列管理器从多个传输请求节点接收这些数据传输请求分组。 请求队列管理器按照优先级排序传输请求数据包，并将其存储在队列管理器内存中。 请求队列管理器根据优先级和优先级别先进先出，处理将传送请求分组分派到空闲数据信道。
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