公开(公告)号：US20130346816A1

公开(公告)日：2013-12-26

申请号：US13532108

申请日：2012-06-25

申请人： Sankaran M. Menon ,  Robert R. Roeder ,  Liwei E. Ju

发明人： Sankaran M. Menon ,  Robert R. Roeder ,  Liwei E. Ju

IPC分类号： G01R31/3177

CPC分类号： G01R31/318575 ,  G01R31/2815 ,  G01R31/31713 ,  G01R31/31717 ,  G01R31/318508 ,  G01R31/318533 ,  G01R31/318572 ,  G01R31/318597 ,  G01R31/31905 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/3278 ,  G06F1/3287

摘要： Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.

摘要翻译： 用于测试具有默认关闭电源的I / O的片上系统（SoC）的输入/输出（I / O）边界扫描链的方法和装置。 一些方法和装置包括实现边界扫描链路旁路路由方案，其选择性地在围绕I / O接口和/或默认关闭的端口的边界扫描链路径路由。 其他技术包括默认情况下，以独立于SoC设施的方式关闭电源的I / O，用于在SoC运行时操作期间控制I / O的电源状态。 各种方案有助于根据IEEE标准1149.1方法进行边界扫描测试。

公开(公告)号：US08904253B2

公开(公告)日：2014-12-02

申请号：US13532108

申请日：2012-06-25

申请人： Sankaran M. Menon ,  Robert R. Roeder ,  Liwei E. Ju

发明人： Sankaran M. Menon ,  Robert R. Roeder ,  Liwei E. Ju

IPC分类号： G01R31/28 ,  G06F11/00 ,  G01R31/3185 ,  G01R31/319 ,  G01R31/317 ,  G06F1/32

CPC分类号： G01R31/318575 ,  G01R31/2815 ,  G01R31/31713 ,  G01R31/31717 ,  G01R31/318508 ,  G01R31/318533 ,  G01R31/318572 ,  G01R31/318597 ,  G01R31/31905 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/3278 ,  G06F1/3287

摘要： Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.

摘要翻译： 用于测试具有默认关闭电源的I / O的片上系统（SoC）的输入/输出（I / O）边界扫描链的方法和装置。 一些方法和装置包括实现边界扫描链路旁路路由方案，其选择性地在围绕I / O接口和/或默认关闭的端口的边界扫描链路径路由。 其他技术包括默认情况下，以独立于SoC设施的方式关闭电源的I / O，用于在SoC运行时操作期间控制I / O的电源状态。 各种方案有助于根据IEEE标准1149.1方法进行边界扫描测试。

公开(公告)号：US20140006864A1

公开(公告)日：2014-01-02

申请号：US13536372

申请日：2012-06-28

申请人： Sankaran M. Menon ,  Robert R. Roeder

发明人： Sankaran M. Menon ,  Robert R. Roeder

IPC分类号： G06F11/28

CPC分类号： G11C29/022 ,  G11C11/40 ,  G11C29/06 ,  G11C2029/0401 ,  G11C2029/5602

摘要： Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.

摘要翻译： 实施例通常针对存储器输入/输出（I / O）接口的无触摸应力测试。 存储器件的实施例包括要与动态随机存取存储器（DRAM）耦合的系统元件，所述系统元件包括用于与DRAM连接的存储器接口，所述接口包括驱动器和接收器，存储器控制器， DRAM的控制，以及测试I / O接口的时序应力测试逻辑。

公开(公告)号：US08924786B2

公开(公告)日：2014-12-30

申请号：US13536372

申请日：2012-06-28

申请人： Sankaran M. Menon ,  Robert R. Roeder

发明人： Sankaran M. Menon ,  Robert R. Roeder

IPC分类号： G06F11/00

CPC分类号： G11C29/022 ,  G11C11/40 ,  G11C29/06 ,  G11C2029/0401 ,  G11C2029/5602

摘要： Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.

摘要翻译： 实施例通常针对存储器输入/输出（I / O）接口的无触摸应力测试。 存储器件的实施例包括要与动态随机存取存储器（DRAM）耦合的系统元件，所述系统元件包括用于与DRAM连接的存储器接口，所述接口包括驱动器和接收器，存储器控制器， DRAM的控制，以及测试I / O接口的时序应力测试逻辑。