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    METHOD OF FORMING A LAMINATE STRUCTURE HAVING A PLATED THROUGH-HOLE USING A REMOVABLE COVER LAYER
    3.
    发明申请
    METHOD OF FORMING A LAMINATE STRUCTURE HAVING A PLATED THROUGH-HOLE USING A REMOVABLE COVER LAYER 审中-公开
    使用可拆卸的覆盖层形成具有通孔的层压结构的方法

    公开(公告)号：US20150007933A1

    公开(公告)日：2015-01-08

    申请号：US14312679

    申请日：2014-06-23

    申请人： Sanmina Corporation

    发明人： Shinichi Iketani ,  Dale Kersten

    IPC分类号： H05K3/26 ,  H05K3/42 ,  H05K3/00 ,  H05K1/05 ,  H05K1/03

    摘要： A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.

    摘要翻译： 提供了一种芯或子复合结构，包括在第一导电膜和第二导电膜之间的介电层。 第一导电膜可以包括形成在第一导电层上或耦合到第一导电层的第一可剥离/可移除覆盖层。 第二导电膜可以包括形成在第二导电层上或耦合到第二导电层的第二可剥离/可移除覆盖层。

    Simultaneous and selective wide gap partitioning of via structures using plating resist
    5.
    发明授权
    Simultaneous and selective wide gap partitioning of via structures using plating resist 有权

    公开(公告)号：US10362687B2

    公开(公告)日：2019-07-23

    申请号：US16181180

    申请日：2018-11-05

    申请人： SANMINA CORPORATION

    发明人： Shinichi Iketani ,  Dale Kersten

    IPC分类号： H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H05K1/02

    摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    6.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 审中-公开

    公开(公告)号：US20180098426A1

    公开(公告)日：2018-04-05

    申请号：US15723086

    申请日：2017-10-02

    申请人： SANMINA CORPORATION

    发明人： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, JR.

    IPC分类号： H05K1/11 ,  H05K1/03 ,  H05K3/42

    摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    Method for forming hole plug
    7.
    发明授权
    Method for forming hole plug 有权

    公开(公告)号：US10237983B2

    公开(公告)日：2019-03-19

    申请号：US14998135

    申请日：2015-12-23

    申请人： Sanmina Corporation

    发明人： Shinichi Iketani ,  Dale Kersten

    IPC分类号： H01K3/10 ,  H05K3/42 ,  H05K1/11 ,  H05K3/00

    摘要： A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    Hole plug for thin laminate
    9.
    发明申请
    Hole plug for thin laminate 有权
    用于薄层压板的孔塞

    公开(公告)号：US20160219703A1

    公开(公告)日：2016-07-28

    申请号：US14998135

    申请日：2015-12-24

    申请人： Sanmina Corporation

    发明人： Shinichi Iketani ,  Dale Kersten

    IPC分类号： H05K1/11 ,  H05K3/00

    CPC分类号： H05K3/429 ,  H05K1/116 ,  H05K3/0094 ,  Y10T29/49165

    摘要： A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

    摘要翻译： 提供了一种形成层压结构中的孔塞的方法。 形成层压体结构，在电介质层的第一侧上至少包括介电层和第一导电箔。 在层叠结构中形成未密封或盲孔，从电介质层的第二侧向第一导电箔延伸，并且至少部分地穿过电介质层，孔的孔深孔直径纵横比小于二十（ 20）到一（1）。 在另一个例子中，孔长宽比可以小于一（1）至1（1）。 然后，通过填充油墨可以沉积在孔中。 然后将通孔填充油墨干燥和/或固化以形成孔塞。

    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST
    10.
    发明申请
    SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST 有权
    通过使用耐蚀材料的结构同时选择性的宽带划分

    公开(公告)号：US20140251663A1

    公开(公告)日：2014-09-11

    申请号：US14205337

    申请日：2014-03-11

    申请人： Sanmina Corporation

    发明人： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, Jr.

    IPC分类号： H05K1/11

    CPC分类号： H05K1/115 ,  H05K1/036 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2203/0713 ,  H05K2203/0723

    摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

    摘要翻译： 提供了具有选择性地定位在第一介电层中的第一电介质层和第一电镀抗蚀剂的多层印刷电路板。 可以将第二电镀抗蚀剂选择性地定位在第一电介质层或第二电介质层中，第二电镀抗蚀剂与第一电镀抗蚀剂分离。 通孔延伸穿过第一电介质层，第一电镀抗蚀剂和第二电镀抗蚀剂。 除了沿第一电镀抗蚀剂和第二电镀抗蚀剂之间的长度之外，通孔的内表面镀有导电材料。 这形成了具有与第二通孔段电隔离的第一通路段的分隔电镀通孔。