-
公开(公告)号：US11765827B2
公开(公告)日：2023-09-19
申请号：US16883671
申请日：2020-05-26
申请人： Sanmina Corporation
CPC分类号： H05K1/115 , H05K1/036 , H05K3/42 , H05K1/11 , H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , H05K2203/0713 , H05K2203/0723
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
-
公开(公告)号：US10188001B2
公开(公告)日：2019-01-22
申请号：US14603191
申请日：2015-01-22
申请人： Sanmina Corporation
摘要： The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
-
3.发明申请METHOD OF FORMING A LAMINATE STRUCTURE HAVING A PLATED THROUGH-HOLE USING A REMOVABLE COVER LAYER 审中-公开使用可拆卸的覆盖层形成具有通孔的层压结构的方法公开(公告)号：US20150007933A1
公开(公告)日：2015-01-08
申请号：US14312679
申请日：2014-06-23
申请人： Sanmina Corporation
发明人： Shinichi Iketani , Dale Kersten
摘要： A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.
摘要翻译： 提供了一种芯或子复合结构，包括在第一导电膜和第二导电膜之间的介电层。 第一导电膜可以包括形成在第一导电层上或耦合到第一导电层的第一可剥离/可移除覆盖层。 第二导电膜可以包括形成在第二导电层上或耦合到第二导电层的第二可剥离/可移除覆盖层。
-
4.发明申请公开(公告)号：US20210014980A1
公开(公告)日：2021-01-14
申请号：US17001431
申请日：2020-08-24
申请人： Sanmina Corporation
发明人： Shinichi Iketani , Dale Kersten
IPC分类号： H05K3/42
摘要： A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.
-
公开(公告)号：US10446356B2
公开(公告)日：2019-10-15
申请号：US15784070
申请日：2017-10-13
申请人： SANMINA CORPORATION
IPC分类号： H01H85/12 , H01H85/055 , H01H85/20 , H01H85/30 , H01H85/56 , H05K1/11 , H05K1/14 , H05K3/00 , H05K3/10 , H05K3/40 , H05K3/46 , H01H85/00 , H01H85/143 , H01H1/58 , H01H85/02 , H05K3/06 , H01H85/06
摘要： A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
-
公开(公告)号：US10362687B2
公开(公告)日：2019-07-23
申请号：US16181180
申请日：2018-11-05
申请人： SANMINA CORPORATION
发明人： Shinichi Iketani , Dale Kersten
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
-
7.发明申请公开(公告)号：US20180098426A1
公开(公告)日：2018-04-05
申请号：US15723086
申请日：2017-10-02
申请人： SANMINA CORPORATION
摘要： A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
-
8.发明授权公开(公告)号：US09661758B2
公开(公告)日：2017-05-23
申请号：US14463588
申请日：2014-08-19
申请人： Sanmina Corporation
CPC分类号： H05K3/427 , H05K3/0026 , H05K3/0047 , H05K2201/09845 , H05K2203/0207 , Y10T29/49165
摘要： Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.
-
9.发明申请公开(公告)号：US20210243903A1
公开(公告)日：2021-08-05
申请号：US17234471
申请日：2021-04-19
申请人： Sanmina Corporation
发明人： Shinichi Iketani , Toshiya Suzuki
摘要： Ultra-thin dielectric printed circuit boards (PCBs) are provided. An ultra-thin dielectric layer may be coupled to a first conductive layer on a first side of the ultra-thin dielectric layer. A second conductive layer may be coupled to a second side of the ultra-thin dielectric layer, and the ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may be patterned to form electrical paths. The patterned second conductive layer may be filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may also be coupled to the second conductive layer.
-
10.发明授权公开(公告)号：US10993333B2
公开(公告)日：2021-04-27
申请号：US16036913
申请日：2018-07-16
申请人： Sanmina Corporation
发明人： Shinichi Iketani , Toshiya Suzuki
摘要： A method for making an ultra-thin dielectric printed circuit board (PCB) is provided. A first side of a first conductive layer is removably coupled to a disposable base. A first ultra-thin dielectric layer and a second conductive layer are laminated to a second side of the first conductive layer, where the first ultra-thin dielectric layer is positioned between the first and second conductive layers, and the first ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may then be patterned to form electrical paths. The patterned second conductive layer is then filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may then be coupled to the second conductive layer. The disposable base may then be detached from the first conductive layer.
-
-
-
-
-
-
-
-
-
搜索结果
35 条记录 (耗时 0.016 秒)
