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    Method and apparatus for detecting multi-hit errors in a cache
    6.
    发明授权
    Method and apparatus for detecting multi-hit errors in a cache 有权
    用于检测高速缓存中的多命中错误的方法和装置

    公开(公告)号：US07337372B2

    公开(公告)日：2008-02-26

    申请号：US10639071

    申请日：2003-08-11

    申请人： Kevin X. Zhang

    发明人： Kevin X. Zhang

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1064 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1032 ,  Y02D10/13

    摘要： Multi-hit errors in a processor cache are detected by a multi-hit detection circuit coupled to the hit lines of the cache. The multi-hit detection circuit compares pairs of hit signals on the hit lines to determine if any two hit signals both indicate a hit. If multiple hits are detected, an error flag indicating the occurrence of multiple hits is generated.

    摘要翻译： 处理器高速缓存中的多命中错误由耦合到高速缓存的命中行的多命中检测电路检测。 多命中检测电路将命中线上的命中信号对进行比较，以确定是否有任何两个命中信号都指示命中。 如果检测到多个命中，则生成指示发生多次命中的错误标志。

    Hybrid low voltage swing sense amplifier
    7.
    发明授权
    Hybrid low voltage swing sense amplifier 有权
    混合低电压摆幅放大器

    公开(公告)号：US06255861B1

    公开(公告)日：2001-07-03

    申请号：US09351140

    申请日：1999-07-12

    申请人： Kevin X. Zhang

    发明人： Kevin X. Zhang

    IPC分类号： G01R1900

    CPC分类号： H03K3/356113

    摘要： A sense amplifier may include a pair of output terminals, an evaluation circuit, a reference circuit and a pair of clamping circuits. The evaluation circuit connects a first output terminal to an evaluation potential. It receives a data signal at an input terminal. The reference circuit connects a second output terminal to the evaluation potential. The reference circuit receives a pair of reference signals on other input terminals. The clamping circuits each couple a respective one of the output terminals to a precharge potential. Inputs of each clamping circuit are coupled to the other of the output terminals.

    摘要翻译： 读出放大器可以包括一对输出端子，评估电路，参考电路和一对钳位电路。 评估电路将第一输出端子连接到评估电位。 它在输入端接收数据信号。 参考电路将第二输出端子连接到评估电位。 参考电路在其他输入端子上接收一对参考信号。 钳位电路各自将输出端子中的相应一个耦合到预充电电位。 每个钳位电路的输入耦合到另一个输出端子。

    Cache column multiplexing using redundant form addresses
    9.
    发明授权
    Cache column multiplexing using redundant form addresses 有权
    使用冗余表单地址进行缓存列复用

    公开(公告)号：US06507531B1

    公开(公告)日：2003-01-14

    申请号：US09538553

    申请日：2000-03-29

    申请人： Kevin X. Zhang

    发明人： Kevin X. Zhang

    IPC分类号： G11C800

    CPC分类号： G11C8/10 ,  G11C15/00

    摘要： A method and apparatus uses possible wordline subsequence identifiers to multiplex columns for addresses received in redundant form, including addresses received from a bypass circuit. A cache wordline decoder uses carry-nonpropagative pre-decode circuitry to identify possible subsequences from redundant addresses. Identified subsequences are combined to identify wordline sequences and to activate corresponding wordline enable signals to access data stored in cache memory. A wordline may correspond to storage locations for multiple addresses. Identified possible subsequences are used to directly multiplex cache columns and the columns are organized so as to guarantee mutual exclusivity.

    摘要翻译： 一种方法和装置使用可能的字线子序列标识符来复用以冗余形式接收的地址的列，包括从旁路电路接收的地址。 缓存字线解码器使用进位非传播预解码电路来识别冗余地址的可能子序列。 识别的子序列被组合以识别字线序列并激活相应的字线使能信号以访问存储在高速缓冲存储器中的数据。 字线可以对应于多个地址的存储位置。 识别的可能子序列用于直接复用高速缓存列，并且列被组织以保证相互排他性。

    Method for evaluating soft error immunity of CMOS circuits
    10.
    发明授权
    Method for evaluating soft error immunity of CMOS circuits 有权
    评估CMOS电路软误差的方法

    公开(公告)号：US06330182B1

    公开(公告)日：2001-12-11

    申请号：US09159466

    申请日：1998-09-23

    申请人： Kevin X. Zhang

    发明人： Kevin X. Zhang

    IPC分类号： G11C1100

    CPC分类号： G11C11/4125 ,  G11C5/005

    摘要： A method for evaluating the robustness of a logic circuit to soft errors involves injecting a current pulse into a node of the logic circuit. The current pulse is shaped to be representative of a high-energy particle strike, and may have an amplitude that is sufficient to momentarily discharge an output node of the logic circuit. The output node of the logic circuit is electrically monitored to determine whether a transition occurs from a first logic state to a second logic state in response to the injected current pulse. In the case where the state of the output node does flip in response to the injected current pulse, a waveform of the injected current pulse is integrated over time to compute a critical charge level (QCRIT). Where the amplitude is insufficient to cause the output node to flip, the amplitude of the injected current pulse is incremented and the above steps are repeated using the incremented amplitude until a logic state transition does occur at the output node.

    摘要翻译： 用于评估逻辑电路对软错误的鲁棒性的方法包括将电流脉冲注入到逻辑电路的节点中。 电流脉冲被成形为代表高能量粒子撞击，并且可以具有足以瞬时放电逻辑电路的输出节点的幅度。 逻辑电路的输出节点被电监控以确定响应于注入的电流脉冲是否从第一逻辑状态到第二逻辑状态发生转变。 在输出节点的状态响应于注入的电流脉冲而翻转的情况下，注入的电流脉冲的波形随时间被积分以计算临界电荷水平（QCRIT）。 在幅度不足以使输出节点翻转的情况下，注入的电流脉冲的幅度增加，并且使用递增幅度重复上述步骤，直到在输出节点处发生逻辑状态转换。