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公开(公告)号：US08618613B2
公开(公告)日：2013-12-31
申请号：US13077681
申请日：2011-03-31
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
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公开(公告)号：US20120248546A1
公开(公告)日：2012-10-04
申请号：US13077681
申请日：2011-03-31
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
摘要翻译： 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。
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公开(公告)号：US20140103448A1
公开(公告)日：2014-04-17
申请号：US14134097
申请日：2013-12-19
申请人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
发明人： Xianghong Tong , Zhanping Chen , Walid M. Hafez , Zhiyong Ma , Sarvesh H. Kulkarni , Kevin X. Zhang , Matthew B. Pedersen , Kevin D. Johnson
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/44 , H01L27/0207 , H01L27/0629 , H01L27/11206 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
摘要翻译： 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。
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公开(公告)号：US20110156801A1
公开(公告)日：2011-06-30
申请号：US12651341
申请日：2009-12-31
申请人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
发明人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
IPC分类号： H01H85/00
CPC分类号： H01L23/5256 , G11C8/20 , G11C17/16 , H01L23/576 , H01L2924/0002 , H01L2924/00
摘要： A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
摘要翻译： 通常提供防篡改保险丝设计。 在这方面，引入一种在集成电路装置中包括多个熔丝的装置，用于存储与熔丝并联的值和多个电阻，其中每个熔丝包括并联电阻器，以提供围绕熔丝的潜在耗散路径。 还描述和要求保护其他实施例。
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公开(公告)号：US08242831B2
公开(公告)日：2012-08-14
申请号：US12651341
申请日：2009-12-31
申请人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
发明人： Xianghong Tong , Zhanping Chen , Kevin X. Zhang , Zhiyong Ma , Kevin D. Johnson , Jun He
IPC分类号： H01H85/02
CPC分类号： H01L23/5256 , G11C8/20 , G11C17/16 , H01L23/576 , H01L2924/0002 , H01L2924/00
摘要： A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.
摘要翻译： 通常提供防篡改保险丝设计。 在这方面，引入一种在集成电路装置中包括多个熔丝的装置，用于存储与熔丝并联的值和多个电阻，其中每个熔丝包括并联电阻器，以提供围绕熔丝的潜在耗散路径。 还描述和要求保护其他实施例。
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公开(公告)号：US08395923B2
公开(公告)日：2013-03-12
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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公开(公告)号：US20100165699A1
公开(公告)日：2010-07-01
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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公开(公告)号：US08101471B2
公开(公告)日：2012-01-24
申请号：US12319104
申请日：2008-12-30
申请人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
发明人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
IPC分类号： H01L21/82
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.
摘要翻译： 可编程抗熔丝元件包括衬底（224），衬底中的N阱（426），在N阱上的电绝缘层（427）以及电绝缘层上的栅电极（430）。 栅电极具有n型掺杂，使得N阱能够在其边界内基本上包含在可编程反熔丝元件的编程事件之后产生的电流。 在相同或另一个实施例中，两次可编程熔丝元件（100）包括金属栅极熔丝（110）和氧化物反熔丝（120），例如刚刚描述的可编程反熔丝元件。
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9.发明申请Programmable fuse and anti-fuse elements and methods of changing conduction states of same 有权可编程保险丝和反熔丝元件以及改变导通状态的方法公开(公告)号：US20100164603A1
公开(公告)日：2010-07-01
申请号：US12319104
申请日：2008-12-30
申请人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
发明人： Walid M. Hafez , Chia-Hong Jan , Jie-Feng Lin , Chetan Prasad , Sangwoo Pae , Zhanping Chen , Anisur Rahman
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.
摘要翻译： 可编程抗熔丝元件包括衬底（224），衬底中的N阱（426），在N阱上的电绝缘层（427）以及电绝缘层上的栅电极（430）。 栅电极具有n型掺杂，使得N阱能够在其边界内基本上包含在可编程反熔丝元件的编程事件之后产生的电流。 在相同或另一个实施例中，两次可编程熔丝元件（100）包括金属栅极熔丝（110）和氧化物反熔丝（120），例如刚刚描述的可编程反熔丝元件。
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公开(公告)号：US20080151593A1
公开(公告)日：2008-06-26
申请号：US11644381
申请日：2006-12-22
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/14 , G11C17/18 , G11C29/816
摘要： An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.
摘要翻译： 本文公开了一种用于熔丝单元阵列的装置，方法和系统。 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。
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