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    Multiplicand shifting in a linear systolic array modular multiplier
    1.
    发明申请
    Multiplicand shifting in a linear systolic array modular multiplier 失效
    线性收缩阵列乘法器中的乘法运算

    公开(公告)号：US20070203961A1

    公开(公告)日：2007-08-30

    申请号：US11242573

    申请日：2005-09-30

    申请人： Sanu Mathew ,  David Harris ,  Ram Krishnamurthy

    发明人： Sanu Mathew ,  David Harris ,  Ram Krishnamurthy

    IPC分类号： G06J1/00

    CPC分类号： G06F7/728 ,  G06F5/01

    摘要： Embodiments of apparatuses and methods for multiplicand shifting in a linear systolic array modular multiplier are disclosed. In one embodiment, an apparatus includes two processing elements of a linear systolic array. One processing element includes multiplication logic, multiplicand shift logic, an adder, modulus logic, and modulus shift logic. The multiplication logic is to multiply a word of the multiplicand and a bit of the multiplier to generate a product. The multiplicand shift logic is to shift the word of the multiplicand. The adder is to add the product to a first running sum to generate a second running sum. The modulus logic is to conditionally add a word of a modulus and the second running sum. The modulus shift logic is to shift the word of the modulus. The next processing element includes logic to multiply the shifted word of the multiplicand and the next bit of the multiplier.

    摘要翻译： 公开了在线性收缩阵列模数乘法器中被乘数移位的装置和方法的实施例。 在一个实施例中，装置包括线性收缩阵列的两个处理元件。 一个处理元件包括乘法逻辑，被乘数移位逻辑，加法器，模数逻辑和模移位逻辑。 乘法逻辑是将被乘数的一个乘法和一个乘法器的乘法乘以产生乘积。 被乘数移位逻辑是移位被乘数的字。 加法器将产品加到第一个运行总和以产生第二个运行总和。 模数逻辑是有条件地添加一个单词的模数和第二个运行总和。 模数移位逻辑是移动模数的单词。 下一个处理元件包括用于乘法被乘数的移位的字和乘法器的下一位的逻辑。

    Native composite-field AES encryption/decryption accelerator circuit
    2.
    发明授权
    Native composite-field AES encryption/decryption accelerator circuit 有权
    本地复合场AES加密/解密加速器电路

    公开(公告)号：US07860240B2

    公开(公告)日：2010-12-28

    申请号：US11771723

    申请日：2007-06-29

    申请人： Sanu Mathew ,  Farhana Sheikh ,  Ram Krishnamurthy

    发明人： Sanu Mathew ,  Farhana Sheikh ,  Ram Krishnamurthy

    IPC分类号： H04K1/10

    CPC分类号： H04L9/0631 ,  H04L2209/12

    摘要： A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).

    摘要翻译： 一种系统包括接收伽罗瓦域GF（2k）的输入数据，将输入数据映射到复合伽罗瓦域GF（2nm），其中k = nm，将映射的输入数据输入到高级加密标准循环函数， 在复合伽罗瓦域GF（2nm）中执行高级加密标准循环函数的两次或更多次迭代的执行，对高级加密标准循环函数的两次或更多次迭代的最后一次的输出数据的接收以及输出数据的映射 到Galois字段GF（2k）。

    Reconfigurable SIMD vector processing system
    3.
    发明申请
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US20080104164A1

    公开(公告)日：2008-05-01

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Multiplier product generation based on encoded data from addressable location
    4.
    发明申请
    Multiplier product generation based on encoded data from addressable location 有权
    基于可寻址位置的编码数据的乘数乘积生成

    公开(公告)号：US20080098278A1

    公开(公告)日：2008-04-24

    申请号：US11540346

    申请日：2006-09-29

    申请人： Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

    发明人： Sanu Mathew ,  Vishak Venkatraman ,  Steven K. Hsu ,  Ram Krishnamurthy

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1006 ,  G06F7/533 ,  G06F7/5332 ,  G06F7/5334 ,  G06F7/74

    摘要： For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，装置包括至少部分地基于对应于第一号码的地址从可寻址位置输出编码数据的第一电路，其中编码数据至少部分地基于对应于第一号码的数据 并且其被编码用于部分产品减少，以及第二电路，用于至少部分地基于编码数据和对应于第二数量的数据来生成产品。 还公开了其他实施例。

    Modular multiplication acceleration circuit and method for data encryption/decryption
    6.
    发明申请
    Modular multiplication acceleration circuit and method for data encryption/decryption 失效
    模块化乘法加速电路和数据加密/解密方法

    公开(公告)号：US20070233772A1

    公开(公告)日：2007-10-04

    申请号：US11393392

    申请日：2006-03-30

    申请人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    发明人： Sanu Mathew ,  Ram Krishnamurthy ,  Zheng Guo

    IPC分类号： G06F7/52

    CPC分类号： G06F7/728 ,  G06F7/722

    摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.

    摘要翻译： 处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否 如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M， 并且产生Z的位2 w-1：w，并将模数M的位2 w-1：w相加到乘积Z的位2 w-1：w，如果 乘积Z的最低有效位为1.乘以X的最低有效位和Y的位2 w-1：w可以至少部分同时与X的最低有效位乘以最小有效位W 确定产品Z的最低有效位是否为1，并将模数M的最低有效W位加到第 如果产品Z的最低有效位为1，则产品Z的最低有效w位。

    Adder circuit with sense-amplifier multiplexer front-end
    7.
    发明申请
    Adder circuit with sense-amplifier multiplexer front-end 有权
    加法器电路带有读出放大器多路复用器前端

    公开(公告)号：US20050125481A1

    公开(公告)日：2005-06-09

    申请号：US10728127

    申请日：2003-12-04

    申请人： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    发明人： Sanu Mathew ,  Mark Anders ,  Ram Krishnamurthy ,  Sapumal Wijeratne

    IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507

    CPC分类号： G06F7/507 ,  G06F7/506

    摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

    摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

    PRIORITY-BASED ROUTING
    9.
    发明申请
    PRIORITY-BASED ROUTING 有权
    优先级路由

    公开(公告)号：US20150188829A1

    公开(公告)日：2015-07-02

    申请号：US14141356

    申请日：2013-12-26

    申请人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    发明人： Sudhir Satpathy ,  Himanshu Kaul ,  Mark Anders ,  Sanu Mathew ,  Gregory Chen ,  Ram Krishnamurthy

    IPC分类号： H04L12/833 ,  H04L12/933 ,  H04L12/725

    CPC分类号： H04L47/2458 ,  H04L45/30 ,  H04L47/56 ,  H04L47/6275 ,  H04L49/109

    摘要： Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.

    摘要翻译： 这里公开了配置用于基于优先级路由的路由器。 路由器被配置为接收多个分组，其中每个分组被分配优先级值。 路由器包括配置为选择具有最高优先级值的分组的输出电路。 输出电路被配置为将所选择的分组的优先级值转发给第二路由器。 输出电路被配置为当第一路由器和第二路由器之间的链路可用时将所选择的分组传送到第二路由器。