公开(公告)号：US06313775B1

公开(公告)日：2001-11-06

申请号：US09652749

申请日：2000-08-31

Applicant: Saska Lindfors ,  Kari Halonen

Inventor： Saska Lindfors ,  Kari Halonen

IPC: H03M382

CPC classification number: H03M3/424 ,  H03M1/167

Abstract: A delta-sigma modulator for converting an analog input signal into a digital output signal comprises a modulator input (501) and a first analog to digital converter (504) coupled to the modulator input (501). The first analog to digital converter has a first analog input and a first digital output. The delta-sigma modulator further comprises an error quantization unit (505, 506, 507) coupled to the first digital output for determining the quantization error caused by the first analog to digital converter (504). Additionally it comprises first signal combining means (508, 708, 802) for combining the outputs of the first analog to digital converter and said error quantization unit to form the digital output signal.

Abstract translation: 用于将模拟输入信号转换为数字输出信号的Δ-Σ调制器包括耦合到调制器输入（501）的调制器输入（501）和第一模数转换器（504）。 第一模数转换器具有第一模拟输入和第一数字输出。 Δ-Σ调制器还包括耦合到第一数字输出的误差量化单元（505,506,507），用于确定由第一模数转换器（504）引起的量化误差。 另外，它包括用于组合第一模数转换器和所述误差量化单元的输出以形成数字输出信号的第一信号组合装置（508,708,802）。

公开(公告)号：US06438366B1

公开(公告)日：2002-08-20

申请号：US09316357

申请日：1999-05-21

Applicant: Saska Lindfors ,  Aarno Pärssinen ,  Kari Halonen

Inventor： Saska Lindfors ,  Aarno Pärssinen ,  Kari Halonen

IPC: H03H1702

CPC classification number: H03H19/004 ,  H03H17/0291

Abstract: Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.

Abstract translation: 电路（300,500,800,900）具有输入（301,501,801,802,901,902）和输出（311,502，OUT，I-OUT，Q-OUT）。 电路对耦合到具有一定输入频率的输入的输入信号进行采样，并将输入信号转换成输出端的某一输出频率，输出频率低于输入频率。 它包括耦合到输入的第一采样器电路（302,510,803,910），耦合到输入的第二采样器电路（303,520,804,920），缓冲部件（309,509,809,903,904） ）耦合到输出和缓冲器切换装置（305-307,514,515,811-818,914,915,924,925,934,935,944,945,954,955,964,965,974,975,984,984 缓冲器切换装置被布置成通过将所述第一采样器电路和所述第二采样器电路耦合到所述缓冲部件来响应缓冲命令（fs / N，A，B）。

公开(公告)号：US06453309B1

公开(公告)日：2002-09-17

申请号：US09310640

申请日：1999-05-12

Applicant: Asko Kananen ,  Ari Paasio ,  Saska Lindfors ,  Kari Halonen

Inventor： Asko Kananen ,  Ari Paasio ,  Saska Lindfors ,  Kari Halonen

IPC: G06F9445

CPC classification number: H03M1/0809 ,  H03M1/365

Abstract: The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.

Abstract translation: 本发明涉及用于校正并行模数转换中的误差的方法和校正器​​（IC6）。 这种可校正误差是由转换器中的并行比较元件（IC1，IC2，IC3，IC4）的状态读数的不确定性引起的，所述不确定性是由诸如非同时状态锁存之类的非等级引起的。 使用非线性细胞神经网络来校正该误差，优选地，通过比较元件（IC1，IC2，IC3，IC4）比较元件（IC1，IC2，IC3，IC4）比较的现象的实际水平是通过估计与比较元件（IC1， ，IC2，IC3，IC4）在时间上或其他方式错误地读取。

公开(公告)号：US07257609B1

公开(公告)日：2007-08-14

申请号：US10399178

申请日：2000-10-16

Applicant: Marko Kosunen ,  Kari Halonen

Inventor： Marko Kosunen ,  Kari Halonen

IPC: G06F15/00 ,  G06F7/52

CPC classification number: G06F7/5272 ,  G06F5/015 ,  G06F7/533 ,  G06F9/3001 ,  G06F9/30025

Abstract: The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.

Abstract translation: 本发明提出一种乘法器装置，其在时间上（不是并行）串行地执行两个不同功率的乘法，以便进一步减小硬件实现所需的面积。 由此，能够仅使用与乘法相关的一个加法器，这有助于降低硬件量并减少硬件所需的面积。 基于二进制加权移位的移位装置用于与乘法相关的移位，从而减少所需的硬件量（多路复用器和硬连线移位元件的数量），从而进一步减少硬件实现的面积。 本发明可以用于使用数字乘法的应用中，例如在数字信号处理DSP，数字滤波器和/或有限脉冲响应滤波器FIR滤波器以及可编程和/或自适应数字滤波器中。 由于在CSD编码中表示乘法器，可以减少必要的移位操作的数量，并且可以减少必要的相加次数，从而有助于减少移位装置的硬件实现所需的面积和硅上的乘法器装置 芯片。

公开(公告)号：US06373317B1

公开(公告)日：2002-04-16

申请号：US09582694

申请日：2000-10-25

Applicant: Pekka Kostiainen ,  Kari Halonen ,  Tuomas Huikko

Inventor： Pekka Kostiainen ,  Kari Halonen ,  Tuomas Huikko

IPC: G06F744

CPC classification number: G06G7/164

Abstract: An IC multiplier circuit has four cells having bipolar transistors to give an exponential input-output function. Each cell has a squaring bipolar transistor and an emitter follower. Differential output signals are taken from the squaring bipolar transistor. The voltage follower is an emitter follower with the bias current through it is substantially larger, e.g. about 10 times larger, than the bias current through the squaring bipolar transistor, which has an emitter resistor.

Abstract translation: IC乘法器电路具有四个具有双极晶体管的单元以产生指数输入 - 输出功能。 每个单元具有平方双极晶体管和射极跟随器。 差分输出信号取自平方双极晶体管。 电压跟随器是射极跟随器，通过其的偏置电流基本上较大，例如， 比通过具有发射极电阻的平方双极晶体管的偏置电流大约10倍。

公开(公告)号：US20130113533A1

公开(公告)日：2013-05-09

申请号：US13642388

申请日：2011-04-20

Applicant: Lasse Aaltonen ,  Jakub Gronicz ,  Kari Halonen

Inventor： Lasse Aaltonen ,  Jakub Gronicz ,  Kari Halonen

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L1/02 ,  H03L7/099 ,  H03L7/23 ,  H03L7/235

Abstract: A temperature compensated frequency reference comprising first MEMS oscillator (MEMS1) used as frequency reference oscillator (REF) for phase locked loop, and means for temperature compensation of phase locked loop output frequency (Fout), wherein the phase locked loop comprises a second MEMS oscillator (MEMS2) used as electronically controlled oscillator (VCO) of phase locked loop.

Abstract translation: 包括用作锁相环的频率参考振荡器（REF）的第一MEMS振荡器（MEMS1）和锁相环输出频率（Fout）的温度补偿装置的温度补偿频率参考，其中锁相环包括第二MEMS振荡器 （MEMS2）用作锁相环的电子控制振荡器（VCO）。