Method and apparatus for extending a software gadget
    1.
    发明授权
    Method and apparatus for extending a software gadget 有权
    用于扩展软件小工具的方法和装置

    公开(公告)号:US08196097B1

    公开(公告)日:2012-06-05

    申请号:US11713412

    申请日:2007-03-02

    IPC分类号: G06F9/44

    CPC分类号: G06F9/44526

    摘要: One embodiment of the present invention provides a system for extending a gadget. During operation, the system initially executes a gadget extension which extends a host gadget. In doing so, the system obtains from the gadget extension a specifier for the host gadget and a specifier for an interface. Next, the system establishes a communication interface between the gadget extension and the host gadget through the interface. Finally, the system uses functionality of the host gadget within the gadget extension via communication through the communication interface.

    摘要翻译: 本发明的一个实施例提供一种用于扩展小工具的系统。 在操作期间,系统最初执行扩展主机小工具的小工具扩展。 在这样做时,系统从小工具扩展中获取主机小工具的说明符和接口的说明符。 接下来,系统通过接口在小工具扩展和主机小配件之间建立通信接口。 最后,该系统通过通信接口通过通信来使用小工具扩展内的主机小配件的功能。

    Starch-reducing rice cooker
    2.
    发明授权
    Starch-reducing rice cooker 失效
    淀粉减少电饭煲

    公开(公告)号:US07388174B2

    公开(公告)日:2008-06-17

    申请号:US10729744

    申请日:2003-12-05

    摘要: A starch-reducing rice cooker includes a pot containing a lower compartment and an upper boiling chamber having a top opening. A partition separates the lower compartment from the upper boiling chamber. A perforated basket is located within the upper boiling chamber for containing rice to be cooked, and is adapted to contain more than sufficient water to immerse the rice for cooking. A cover is provided. In one embodiment, the cover is also provided with a top opening having a sprayer, spraying cool rinsing water onto the rice within the basket, after cooking of the rice is complete. A discharge valve within the partition communicates between the upper boiling water chamber and the lower compartment. A detector is programmed to detect when boiling of water in the upper boiling temperature starts and to maintain boiling for a time required to properly cook the rice based upon the boiling temperature of the water. The discharge valve is activated after cooking is completed for discharging water through the discharge valve from the upper boiling chamber into the lower compartment, thereby reducing the starch content of the cooked rice.

    摘要翻译: 淀粉还原电饭煲包括一个包含下部隔间的锅和一个具有顶部开口的上部沸腾室。 隔板将下隔室与上部沸腾室隔开。 多孔的篮子位于上部沸腾室内,用于容纳要煮熟的米饭,并且适于含有足够的水以将米饭浸泡以进行烹饪。 提供盖子。 在一个实施例中,盖子还设置有具有喷雾器的顶部开口,在完成饭的烹饪之后,将清洗水喷洒到篮子内的米上。 隔板内的排放阀在上部沸水室和下部隔室之间连通。 检测器被编程为检测在沸腾温度开始时水的沸腾何时开始,并且基于水的沸腾温度保持煮沸以适当地煮饭所需的时间。 在完成烹饪完成之后,排出阀通过排出阀从上部沸腾室排入下部室,从而降低了米饭的淀粉含量。

    Methods and systems for interfacing applications with a search engine
    3.
    发明申请
    Methods and systems for interfacing applications with a search engine 审中-公开
    用于将应用程序与搜索引擎进行接口的方法和系统

    公开(公告)号:US20050234929A1

    公开(公告)日:2005-10-20

    申请号:US10814387

    申请日:2004-03-31

    IPC分类号: G06F7/00 G06F17/30

    摘要: The present invention provides an application interface for a unified search engine. In one embodiment, an event schema is determined for an application, wherein the application has associated articles, event data is determined for an event, based at least in part on the event schema, wherein the event relates to user interactions with an article associated with the application, event data is transferred to a search application and stored in a searchable database, wherein the events and articles associated with the application are searchable by a search application.

    摘要翻译: 本发明提供了一种用于统一搜索引擎的应用接口。 在一个实施例中,为应用确定事件模式,其中应用具有相关联的文章,事件数据至少部分地基于事件模式而确定事件数据,其中事件涉及与与...相关联的文章的用户交互 将应用程序事件数据传送到搜索应用程序并存储在可搜索数据库中,其中与应用程序相关联的事件和文章可由搜索应用程序搜索。

    Methods and systems for information capture and retrieval
    4.
    发明申请
    Methods and systems for information capture and retrieval 有权
    用于信息捕获和检索的方法和系统

    公开(公告)号:US20050234848A1

    公开(公告)日:2005-10-20

    申请号:US10881584

    申请日:2004-06-30

    IPC分类号: G06F7/00 G06F17/30

    CPC分类号: G06F17/30864

    摘要: Systems and methods that identify and extract information from articles are described. In one embodiment, a search engine implements a method comprising capturing an event in real time upon the occurrence of the event, wherein the event comprises a user interaction with an article on a client device, wherein the article is capable of being associated with at least one of a plurality of client applications, determining if the event should be indexed, and if the event should be indexed, indexing the event and storing the event and at least a portion of content associated with the article.

    摘要翻译: 描述了从文章中识别和提取信息的系统和方法。 在一个实施例中,搜索引擎实现一种方法,包括在事件发生时实时捕获事件,其中事件包括与客户端设备上的物品的用户交互,其中该物品能够至少与 多个客户应用程序之一,确定事件是否应被索引,以及如果事件应被索引,索引事件并存储事件以及与该文章相关联的内容的至少一部分。

    Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability
    5.
    发明申请
    Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability 有权
    测试点,部分扫描和全扫描触发器插入的光谱和信息理论方法,以提高集成电路可测试性

    公开(公告)号:US20100102825A1

    公开(公告)日:2010-04-29

    申请号:US12454476

    申请日:2009-05-18

    IPC分类号: G01R31/02 G06F17/50 H01R43/16

    摘要: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

    摘要翻译: 描述了使用梯度下降和线性规划(LP)算法将测试点(TP)和/或扫描的触发器(SFF)插入大电路以使其可测试的可测性(DFT)算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真,香农熵测量(信息理论)和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率(使用数字信号处理(DSP)方法分析))和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量,因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解,并且使用熵测量来最大化通过电路下测试(CUT)的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。

    Method and system for proportionalizing costs for a transaction
    6.
    发明申请
    Method and system for proportionalizing costs for a transaction 审中-公开
    交易成本成比例的方法和系统

    公开(公告)号:US20060074762A1

    公开(公告)日:2006-04-06

    申请号:US10950060

    申请日:2004-09-24

    IPC分类号: G06Q30/00

    摘要: The invention concerns a method (300) for proportionalizing costs for a transaction. The method includes the steps of determining (312) a subtransactional selling price (410), a corresponding subtransactional quantity (420) and a total transactional amount (430), dividing (314) the product of the subtransactional selling price and the corresponding subtransactional quantity by the total transactional amount and multiplying (316) an amount determined from the dividing step by a transactional cost associated with the transaction to generate a proportionalized cost.

    摘要翻译: 本发明涉及一种用于交易成本成比例的方法(300)。 该方法包括以下步骤:确定(312)子交易销售价格(410),对应的子交易量(420)和总交易量(430),除以(314)子交易销售价格的乘积和相应的子交易量 通过总交易量并将从划分步骤确定的金额与交易相关联的交易成本乘以(316)以产生成比例的成本。

    Methods and systems for structuring event data in a database for location and retrieval
    7.
    发明申请
    Methods and systems for structuring event data in a database for location and retrieval 审中-公开
    用于在数据库中构造事件数据以进行位置和检索的方法和系统

    公开(公告)号:US20050223027A1

    公开(公告)日:2005-10-06

    申请号:US10815071

    申请日:2004-03-31

    IPC分类号: G06F7/00 G06F17/30

    CPC分类号: G06F16/90

    摘要: Methods and systems are provided for configuring event data representing activity within a computer, which allows that article to be more readily accessed by a search engine. In one embodiment, an event associated with an article is captured, wherein the event comprises event data, the event is indexed, a related event object is created related to the event, wherein the related event object comprises a set of one or more related events, and the related event object is associated with the one or more related events.

    摘要翻译: 提供了用于配置表示计算机内的活动的事件数据的方法和系统,这允许该文章被搜索引擎更容易地访问。 在一个实施例中,捕获与物品相关联的事件,其中所述事件包括事件数据,所述事件被索引,创建与所述事件相关的相关事件对象,其中所述相关事件对象包括一组或多个相关事件 ,并且相关事件对象与一个或多个相关事件相关联。

    Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability
    10.
    发明授权
    Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability 有权
    测试点,部分扫描和全扫描触发器插入的光谱和信息理论方法,以提高集成电路可测试性

    公开(公告)号:US08164345B2

    公开(公告)日:2012-04-24

    申请号:US12454476

    申请日:2009-05-18

    IPC分类号: G01R31/02 G01R31/28 G06F17/50

    摘要: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

    摘要翻译: 描述了使用梯度下降和线性规划(LP)算法将测试点(TP)和/或扫描的触发器(SFF)插入大电路以使其可测试的可测性(DFT)算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真,香农熵测量(信息理论)和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率(使用数字信号处理(DSP)方法分析))和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量,因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解,并且使用熵测量来最大化通过电路下测试(CUT)的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。