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公开(公告)号：US06321313B1
公开(公告)日：2001-11-20
申请号：US09300769
申请日：1999-04-27
申请人： Satoki Ishii , Yoshitsugu Inoue , Masahiro Yamada , Toru Noro
发明人： Satoki Ishii , Yoshitsugu Inoue , Masahiro Yamada , Toru Noro
IPC分类号： G06F1216
摘要： A determining unit determines which area in an SDRAM is the area in which image data is stored. According to the determination of the determining unit, a control unit activates a power-down mode only for an area in the SDRAM, the image data being stored in the area. In order to determine whether or not the data stored in the SDRAM is image data, a code is previously added to the relevant data. Whether or not the relevant data stored in the SDRAM is image data is determined by the determining unit using the added code. A minimum of only one bit does well as the code for determining whether or not the data stored in the SDRAM is image data. Instead of previously adding a code to relevant data, it is also possible, for the same purpose, to store a code in an internal register of the SDRAM, the code indicating contents of data stored in the SDRAM.
摘要翻译： 确定单元确定SDRAM中的哪个区域是存储图像数据的区域。 根据确定单元的确定，控制单元仅为SDRAM中的区域启动掉电模式，图像数据被存储在该区域中。 为了确定存储在SDRAM中的数据是否是图像数据，先前将代码添加到相关数据。 存储在SDRAM中的相关数据是否是图像数据由确定单元使用添加的代码来确定。 只有一位的最小值与确定SDRAM中存储的数据是否为图像数据的代码一样。 代替以前向相关数据添加代码，为了相同的目的，也可以将代码存储在SDRAM的内部寄存器中，代码指示存储在SDRAM中的数据的内容。
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公开(公告)号：US5923829A
公开(公告)日：1999-07-13
申请号：US514863
申请日：1995-08-14
申请人： Satoki Ishii , Yoshitsugu Inoue , Masahiro Yamada , Toru Noro
发明人： Satoki Ishii , Yoshitsugu Inoue , Masahiro Yamada , Toru Noro
IPC分类号： G11C5/00 , H01L27/108 , G06F1/30 , G06F1/32
摘要： A determining unit determines which area in an SDRAM is the area in which image data is stored. According to the determination of the determining unit, a control unit activates a power-down mode only for an area in the SDRAM, the image data being stored in the area. In order to determine whether or not the data stored in the SDRAM is image data, a code is previously added to the relevant data. Whether or not the relevant data stored in the SDRAM is image data is determined by the determining unit using the added code. A minimum of only one bit does well as the code for determining whether or not the data stored in the SDRAM is image data. Instead of previously adding a code to relevant data, it is also possible, for the same purpose, to store a code in an internal register of the SDRAM, the code indicating contents of data stored in the SDRAM.
摘要翻译： 确定单元确定SDRAM中的哪个区域是存储图像数据的区域。 根据确定单元的确定，控制单元仅为SDRAM中的区域启动掉电模式，图像数据被存储在该区域中。 为了确定存储在SDRAM中的数据是否是图像数据，先前将代码添加到相关数据。 存储在SDRAM中的相关数据是否是图像数据由确定单元使用添加的代码来确定。 只有一位的最小值与确定SDRAM中存储的数据是否为图像数据的代码一样。 代替以前向相关数据添加代码，为了相同的目的，也可以将代码存储在SDRAM的内部寄存器中，代码指示存储在SDRAM中的数据的内容。
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3.发明授权Geometrical operation apparatus for performing high speed calculations in a three-dimensional computer graphic display system 失效用于在三维计算机图形显示系统中执行高速计算的几何运算装置
公开(公告)号：US6005590A
公开(公告)日：1999-12-21
申请号：US743178
申请日：1996-11-05
CPC分类号： G06T1/20
摘要： The apparatus comprises an input memory 102 for storing data necessary for geometrical operations, such as coordinate transformation, luminance calculation, and clipping operation of graphics; a global bus connected to the input memory; a plurality of floating process memories connected to the global bus, for receiving data necessary for geometrical operations; a sequencer for transmitting data necessary for geometrical operations, stored in the input memory, to the plurality of floating process memories; and a plurality of floating processing units each connected to a respective one of the plurality of floating process memories, for independently executing geometrical operations, using data transmitted from the floating process memories.
摘要翻译： 该装置包括用于存储几何运算所必需的数据的输入存储器102，例如坐标变换，亮度计算和图形的剪切操作; 连接到输入存储器的全局总线; 连接到全局总线的多个浮动处理存储器，用于接收几何操作所需的数据; 定序器，用于将存储在输入存储器中的几何运算所需的数据发送到多个浮动处理存储器; 以及多个浮动处理单元，每个浮动处理单元都连接到多个浮动处理存储器中的相应一个浮动处理存储器，用于使用从浮动处理存储器发送的数据来独立地执行几何操作。
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4.发明授权Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权能够并行执行输入/输出和高速几何计算处理的几何处理器公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译： 几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。 几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点 功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。
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公开(公告)号：US5673422A
公开(公告)日：1997-09-30
申请号：US376618
申请日：1995-01-23
IPC分类号： G09G5/00 , G06F12/08 , G06T1/20 , G06T3/00 , G06T11/00 , G06T15/10 , G09G5/39 , G09G5/393 , G11C11/401 , G06F15/76
摘要： A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.
摘要翻译： 帧缓冲存储器包括DRAM的主存储器，SRAM的高速缓冲存储器，用于传送256位数据的第一传输总线，例如主存储器和高速缓冲存储器之间的像素处理单元，用于执行 根据从高速缓冲存储器提供的数据和外部应用数据的预定操作处理，用于将从高速缓存存储器提供的数据与外部应用数据进行比较的比较单元，用于将数据从高速缓冲存储器传送到像素处理单元的传输总线，以及 比较单元，用于将结果数据从像素处理单元传送到高速缓冲存储器的传送总线，以及用于存储从主存储器读出的数据的串行存取存储器，并将所存储的数据串行地提供给外部世界。 根据该结构，图形所需的alpha混合处理，光栅操作，Z比较处理等可以灵活地高速地进行。
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6.发明授权
公开(公告)号：US5657485A
公开(公告)日：1997-08-12
申请号：US509940
申请日：1995-08-01
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F9/30065
摘要： The present invention is directed to a program control unit which enables a program control to achieve an efficient loop processing which does not immediately follow a loop instruction and which contains a start address and end address. In the program control unit, the start address and end address of a loop processing are stored in a register (start) (7) and a register (end) (8), respectively, in synchronization with a clock t1. The stored data "start" of the register (7) and the stored data "end" of the register (8) are inputted to a comparator (12) and a comparator (11), respectively. The comparator (12) compares the output from a delay program counter (18) with the data "start", and sets a flag f start when the comparison result indicates agreement and otherwise resets it. The comparator (11) compares the output from a delay program counter (18) with the data "end", and sets a flag f end when the comparison result indicates agreement and otherwise resets it.
摘要翻译： 本发明涉及一种程序控制单元，其使得程序控制能够实现不立即循环指令并且包含开始地址和结束地址的有效的循环处理。 在程序控制单元中，循环处理的起始地址和结束地址分别与时钟t1同步地存储在寄存器（起始）（7）和寄存器（结束）（8）中。 寄存器（7）的存储数据“开始”和寄存器（8）的存储数据“结束”分别输入到比较器（12）和比较器（11）。 比较器（12）将来自延迟程序计数器（18）的输出与数据“开始”进行比较，并且当比较结果指示一致时设置标志f开始，否则将其复位。 比较器（11）将来自延迟程序计数器（18）的输出与数据“结束”进行比较，并且当比较结果表示协议时设定标志f结束，否则将其复位。
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公开(公告)号：US07054979B2
公开(公告)日：2006-05-30
申请号：US09985009
申请日：2001-11-01
IPC分类号： G06F13/14
CPC分类号： H04L12/4625
摘要： The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.
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8.发明授权公开(公告)号：US07038684B2
公开(公告)日：2006-05-02
申请号：US10200253
申请日：2002-07-23
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
CPC分类号： G06T15/005
摘要： An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.
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9.发明申请公开(公告)号：US20060001670A1
公开(公告)日：2006-01-05
申请号：US11218774
申请日：2005-09-06
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.
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10.发明申请Assembler capable of reducing size of object code, and processor for executing the object code 审中-公开能够减少对象代码大小的汇编器和用于执行目标代码的处理器公开(公告)号：US20050108698A1
公开(公告)日：2005-05-19
申请号：US10841467
申请日：2004-05-10
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.
摘要翻译： 指令分析单元顺序地分析输入到程序输入单元的程序的指令。 NOP指令分析部分将连续的NOP指令编码为一个连续的NOP指令。 指令代码输出单元将由指令分析单元编码的指令作为目标代码输出。 因此，可以减少目标代码的大小。
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