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    Integrated circuit device and electronic instrument
    1.
    发明授权
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US07782694B2

    公开(公告)日：2010-08-24

    申请号：US11477716

    申请日：2006-06-30

    申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    IPC分类号： G11C7/00

    CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2360/18

    摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

    摘要翻译： 集成电路装置包括显示存储器和数据读取控制电路。 数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。 显示存储器包括分别与多个位线连接的多个读出放大器单元。 分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向） 。

    Integrated circuit device and electronic instrument
    2.
    发明授权
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US07613066B2

    公开(公告)日：2009-11-03

    申请号：US11477719

    申请日：2006-06-30

    申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    IPC分类号： G11C8/00

    CPC分类号： G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2360/12

    摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

    摘要翻译： 在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。 当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。 （M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动器单元设置在 第三个细分驱动程序。

    Integrated circuit device and electronic instrument
    3.
    发明申请
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US20070013707A1

    公开(公告)日：2007-01-18

    申请号：US11477719

    申请日：2006-06-30

    申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    IPC分类号： G09G5/36

    CPC分类号： G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2360/12

    摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

    摘要翻译： 在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。 当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。 （M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动单元 第三个细分驱动程序。

    Integrated circuit device and electronic instrument
    5.
    发明申请
    Integrated circuit device and electronic instrument 有权
    集成电路器件和电子仪器

    公开(公告)号：US20070013687A1

    公开(公告)日：2007-01-18

    申请号：US11477716

    申请日：2006-06-30

    申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

    IPC分类号： G09G5/00

    CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2360/18

    摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

    摘要翻译： 集成电路装置包括显示存储器和数据读取控制电路。 数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。 显示存储器包括分别与多个位线连接的多个读出放大器单元。 分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向） 。

    Integrated circuit device and electronic instrument
    9.
    发明申请
    Integrated circuit device and electronic instrument 审中-公开
    集成电路器件和电子仪器

    公开(公告)号：US20070013635A1

    公开(公告)日：2007-01-18

    申请号：US11477742

    申请日：2006-06-30

    申请人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

    发明人： Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa ,  Noboru Itomi ,  Satoru Kodaira ,  Junichi Karasawa ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3674 ,  G09G3/3685

    摘要： An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.

    摘要翻译： 集成电路装置包括数据驱动块DB，存储块MB和逻辑电路块LB。 数据驱动器块DB包括数据驱动器DR和缓冲电路BF，其缓冲来自逻辑电路块LB的驱动器控制信号，并将缓冲的驱动器控制信号输出到数据驱动器DR。 存储块MB包括选择字线的存储单元阵列MA和行地址解码器RD。 数据驱动块DB和存储块MB沿着方向D1设置，缓冲电路BF和数据驱动器DR沿着方向D 2设置，行地址解码器RD和存储单元阵列MA沿着 方向D 2，并且缓冲电路BF和行地址解码器RD沿着方向D1设置。