公开(公告)号：US5586078A

公开(公告)日：1996-12-17

申请号：US528306

申请日：1995-09-14

申请人： Satoru Takase ,  Kiyofumi Sakurai ,  Masaki Ogihara

发明人： Satoru Takase ,  Kiyofumi Sakurai ,  Masaki Ogihara

IPC分类号： G11C11/401 ,  G06F12/08 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G06F12/0893 ,  G11C11/4091 ,  G11C11/4096

摘要： A DRAM includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.

摘要翻译： DRAM包括以共享读出放大器配置划分的形式的存储器块，其中用作高速缓冲存储器的子阵列和读出放大器在存储器芯片的X方向上交替排列。 存储块沿Y方向排列。 数据线与对应的子阵列的Y方向平行地形成，用于传送保持在与子阵列相对应的读出放大器中的数据。 I / O焊盘与X方向平行布置，用于经由数据线向/从相应的子阵列输入/输出数据。 当在DRAM的小区域中实现共享读出放大器配置和读出放大器缓存系统时，高速缓冲存储器的命中率增加，并且可以通过缩短存储芯片中形成的数据路径来高速传输数据。

公开(公告)号：USRE37427E1

公开(公告)日：2001-10-30

申请号：US09493001

申请日：2000-01-27

申请人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

发明人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

IPC分类号： G11C1300

CPC分类号： G11C7/1012 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1006 ,  G11C11/4093 ,  G11C11/4096

摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

摘要翻译： 在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。 每个子阵列设置有与字线并行形成的数据线。 数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。 这种布置允许数据路径被缩短并且能够高速传送数据。

公开(公告)号：US5642326A

公开(公告)日：1997-06-24

申请号：US534558

申请日：1995-09-27

申请人： Kiyofumi Sakurai ,  Satoru Takase ,  Masaki Ogihara

发明人： Kiyofumi Sakurai ,  Satoru Takase ,  Masaki Ogihara

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C8/18

摘要： A dynamic memory comprises a control circuit for controlling the selection of the row decoder and the activation of the sense amplifiers in accordance with a RAS signal externally supplied thereto and a word line control circuit for controlling a selected word line to turn the electric potentials read out from the memory cells connected to the word line on the bit lines connected to the respective memory cells back to an inactive level after the electric potentials are sensed and amplified by the sense amplifiers corresponding to the respective bit lines during the time period from the time when the RAS signal is turned to an active level and the time when it is turned back to the inactive level. A dynamic memory has gate oxide films are designed to be subjected to a less electric field strength in order to minimize the degradation of reliability and the memory can effectively reduce the fall of the word line driving stepped-up voltage to eliminate the necessity of a leak current compensation circuit. Additionally, the memory reduces the time required to restore the electric potentials for a data reading operation and also the cycle time required for a data writing operation.

摘要翻译： 动态存储器包括控制电路，用于根据外部提供给它的+ E，ovs RAS + EE信号和用于控制选定字线的字线控制电路来控制行解码器的选择和感测放大器的激活 将连接到各个存储器单元的位线上连接到字线的存储单元读出的电位在由该位线对应的读出放大器在 从+ E，ovs RAS + EE信号变为有效电平的时间段和其回到无效电平的时间。 具有栅极氧化膜的动态存储器被设计为经受较少的电场强度以便最小化可靠性的劣化，并且存储器可以有效地减少字线驱动升压电压的下降以消除泄漏的必要性 电流补偿电路。 此外，存储器减少了恢复数据读取操作的电位所需的时间以及数据写入操作所需的周期时间。

公开(公告)号：US5712827A

公开(公告)日：1998-01-27

申请号：US530725

申请日：1995-09-19

申请人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

发明人： Masaki Ogihara ,  Satoru Takase ,  Kiyofumi Sakurai

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C13/00 ,  G11C11/34

CPC分类号： G11C7/1012 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1006

摘要： In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

摘要翻译： 在动态类型存储器中，存储器单元阵列被划分成存储器芯片上的多个子阵列。 每个子阵列设置有与字线并行形成的数据线。 数据缓冲器和多路复用器电路和I / O焊盘与位线并行布置在存储器芯片的一侧。 这种布置允许数据路径被缩短并且能够高速传送数据。

公开(公告)号：US5410512A

公开(公告)日：1995-04-25

申请号：US64438

申请日：1993-05-21

申请人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

发明人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C7/1021

摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

摘要翻译： 半导体存储器件包括形成在芯片中的硅芯片和子阵列。 在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。 此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。 连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

公开(公告)号：US07863751B2

公开(公告)日：2011-01-04

申请号：US12171650

申请日：2008-07-11

申请人： Satoru Takase

发明人： Satoru Takase

IPC分类号： H01L29/40

CPC分类号： H01L27/24

摘要： A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s).

摘要翻译： 一种半导体集成电路器件，包括：形成有扩散层的半导体衬底; 以及层叠在半导体衬底上方的多层布线，以通过接触插塞连接到扩散层，其中形成在其上的第一布线和第二布线分别经由第一接触插塞和第二接触插塞连接到扩散层，并且 排列成并联的第二接触插塞的数量被设定为大于第一接触插塞的数量。

公开(公告)号：US07808854B2

公开(公告)日：2010-10-05

申请号：US12033198

申请日：2008-02-19

申请人： Satoru Takase

发明人： Satoru Takase

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

摘要翻译： 通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。 在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。 每个读出放大器被配置为选择性地耦合到数据线。 在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器， 第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

公开(公告)号：US20090207679A1

公开(公告)日：2009-08-20

申请号：US12033198

申请日：2008-02-19

申请人： Satoru Takase

发明人： Satoru Takase

IPC分类号： G11C7/08

CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

摘要翻译： 通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。 在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。 每个读出放大器被配置为选择性地耦合到数据线。 在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器， 第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

公开(公告)号：US07573735B2

公开(公告)日：2009-08-11

申请号：US11530271

申请日：2006-09-08

申请人： Satoru Takase ,  Takehito Sasaki

发明人： Satoru Takase ,  Takehito Sasaki

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C5/143 ,  G11C5/147

摘要： Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.

摘要翻译： 用于减少由电压之间的相对变化引起的不稳定性和可编写性问题的系统和方法，其中存储单元和访问存储器单元的逻辑组件通过在电压不在可接受的工作范围内时禁止存储器访问而工作。 一个实施例包括流水线处理器，其具有在第一电压处接收功率的逻辑部件和以第二电压接收功率的一组SRAM单元。 临界条件检测器被配置为监视第一和第二电压并且确定这些电压的比率是否在可接受的范围内。 当电压不在可接受范围内时，产生异常，异常处理程序使处理器流水线停止以禁止对SRAM单元的访问。 当电压返回到可接受的范围时，异常处理程序将恢复流水线并完成异常的处理。

公开(公告)号：US20080249727A1

公开(公告)日：2008-10-09

申请号：US11696381

申请日：2007-04-04

申请人： Satoru Takase

发明人： Satoru Takase

IPC分类号： G01R19/00

CPC分类号： G01R31/3012 ,  G01R31/3004

摘要： Systems and methods for determining local voltages provided by a power distribution network to an integrated circuit chip by applying an external voltage to a power distribution network, firing a set of current sources distributed across the chip and measuring local voltages on the chip. The current sources may, for example, comprise a clock tree carrying a free-running clock signal, or multiple individual current source structures. The voltages may be measured, for instance, by units comprising voltage controlled oscillators (VCO's) coupled to counters which determine the corresponding oscillation frequencies and registers which store the resulting oscillation counts. The measured voltages may be used to identify non-uniformities in the voltage applied across the chip, as well as to determine local differences in the resistance of the power distribution network.

摘要翻译： 通过向配电网络施加外部电压来确定由配电网络向集成电路芯片提供的局部电压的系统和方法，点燃分布在芯片上的一组电流源并测量芯片上的局部电压。 电流源可以例如包括携带自由运行时钟信号的时钟树，或多个单独的电流源结构。 电压可以例如通过耦合到确定相应振荡频率的计数器的压控振荡器（VCO）和存储所得到的振荡计数的寄存器的单元来测量。 测量的电压可用于识别施加在芯片上的电压中的不均匀性，以及确定配电网络的电阻的局部差异。