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    Output buffer circuit and differential output buffer circuit, and transmission method
    1.
    发明授权
    Output buffer circuit and differential output buffer circuit, and transmission method 有权
    输出缓冲电路和差分输出缓冲电路及其传输方式

    公开(公告)号：US07692445B2

    公开(公告)日：2010-04-06

    申请号：US11686560

    申请日：2007-03-15

    申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    IPC分类号： H03K19/003

    CPC分类号： H03K19/018521

    摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

    摘要翻译： 在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能 在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。 选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个 选择器逻辑的选择信号。

    Output buffer circuit and differential output buffer circuit, and transmission method
    2.
    发明授权
    Output buffer circuit and differential output buffer circuit, and transmission method 有权
    输出缓冲电路和差分输出缓冲电路及其传输方式

    公开(公告)号：US08324925B2

    公开(公告)日：2012-12-04

    申请号：US13106926

    申请日：2011-05-13

    申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    IPC分类号： H03K19/003

    CPC分类号： H03K19/018521

    摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

    摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

    Output buffer circuit and differential output buffer circuit, and transmission method
    3.
    发明授权
    Output buffer circuit and differential output buffer circuit, and transmission method 有权
    输出缓冲电路和差分输出缓冲电路及其传输方式

    公开(公告)号：US07969197B2

    公开(公告)日：2011-06-28

    申请号：US12716796

    申请日：2010-03-03

    申请人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    发明人： Satoshi Muraoka ,  Norio Chujo ,  Ritsuro Orihashi

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018521

    摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

    摘要翻译： 输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。 输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。 缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。 通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

    OUTPUT BUFFER CIRCUIT, SIGNAL TRANSMISSION INTERFACE CIRCUIT AND APPARATUS
    5.
    发明申请
    OUTPUT BUFFER CIRCUIT, SIGNAL TRANSMISSION INTERFACE CIRCUIT AND APPARATUS 审中-公开
    输出缓冲电路，信号传输接口电路和设备

    公开(公告)号：US20090003463A1

    公开(公告)日：2009-01-01

    申请号：US12099953

    申请日：2008-04-09

    申请人： Satoshi Muraoka ,  Norio Chujo

    发明人： Satoshi Muraoka ,  Norio Chujo

    IPC分类号： H04B3/00 ,  H03K19/0175

    CPC分类号： H03K19/0005 ,  H03K17/164 ,  H03K19/018521 ,  H04L25/0288 ,  H04L25/03343

    摘要： An output buffer circuit which transmits a logic signal to a transmission line includes a transmission pre-emphasis output circuit and a transmission pre-emphasis amount determination circuit. The transmission pre-emphasis output circuit controls a pre-emphasis amount according to an output signal from the transmission pre-emphasis amount determination circuit. The transmission pre-emphasis amount determination circuit adjusts a pre-emphasis amount and the number of pre-emphasis taps according to a pseudo loss control signal, controls a pre-emphasis amount of a transmission signal so that a signal amplitude is made smaller in a signal component with a high frequency than that of a signal component with a low frequency, and imparts signal degradation to a received waveform to realize transmission loss in a pseudo manner.

    摘要翻译： 向传输线发送逻辑信号的输出缓冲电路包括发送预加重输出电路和发送预加重量确定电路。 发送预加重输出电路根据来自发送预加重量确定电路的输出信号来控制预加重量。 发送预加重量确定电路根据伪损失控制信号调整预加重量和预加重抽头的数量，控制发送信号的预加重量，使信号幅度变小 信号分量高于具有低频率的信号分量的信号分量，并且对接收到的波形施加信号劣化，以伪方式实现传输损耗。

    Test method and interposer used therefor
    7.
    发明授权
    Test method and interposer used therefor 失效
    用于此的测试方法和插入器

    公开(公告)号：US08680881B2

    公开(公告)日：2014-03-25

    申请号：US13044717

    申请日：2011-03-10

    申请人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

    发明人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2889

    摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

    摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

    Data transmission system and semiconductor circuit
    8.
    发明授权
    Data transmission system and semiconductor circuit 有权
    数据传输系统和半导体电路

    公开(公告)号：US08988160B2

    公开(公告)日：2015-03-24

    申请号：US13004609

    申请日：2011-01-11

    申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

    发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

    IPC分类号： H03H2/00 ,  H03H7/38 ,  H04B3/02

    CPC分类号： H04B3/02

    摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

    摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08581622B1

    公开(公告)日：2013-11-12

    申请号：US13512465

    申请日：2012-05-16

    申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

    发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

    IPC分类号： H03K17/16

    CPC分类号： G11C7/10 ,  G11C7/1057 ,  G11C7/1084

    摘要： To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.

    摘要翻译： 与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。 具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。 电阻元件放置在信号互连的任意位置或分支点处。

    Electronic circuit device having a function of inhibiting resonance in power wiring
    10.
    发明授权
    Electronic circuit device having a function of inhibiting resonance in power wiring 失效
    具有抑制电力布线中的谐振功能的电子电路装置

    公开(公告)号：US5844762A

    公开(公告)日：1998-12-01

    申请号：US762691

    申请日：1996-12-12

    申请人： Hideho Yamamura ,  Masakazu Yamamoto ,  Naoki Maru ,  Satoshi Muraoka

    发明人： Hideho Yamamura ,  Masakazu Yamamoto ,  Naoki Maru ,  Satoshi Muraoka

    IPC分类号： H03H7/01 ,  G06F1/26 ,  H03H2/00 ,  H05K1/02 ,  H05K3/46 ,  H05K9/00 ,  H02H3/22

    CPC分类号： H05K1/0234 ,  H05K1/0231 ,  H05K2201/09309 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

    摘要： An electronic circuit device having a power wiring resonance inhibition function includes a plurality of electronic circuit elements, and a wiring board having the electronic circuit elements disposed thereon. The wiring board includes a plurality of planar power supply wires for supplying power to the electronic circuit elements. The planar power wires include a pair of planar power supply wires for supplying power to the electronic circuit elements at a predetermined voltage. The electronic circuit device also includes a plurality of damping elements disposed at a plurality of positions on the wiring board. The damping elements are connected between the pair of planar power supply wires at a plurality of positions on the pair of planar power supply wires. The damping elements reduce power supply system impedance and inhibit power wiring system resonance, thereby reducing supply voltage fluctuation caused by the power wiring system resonance and noise caused by the supply voltage fluctuation.

    摘要翻译： 具有电力线共振抑制功能的电子电路装置包括多个电子电路元件，以及配置有电子电路元件的布线基板。 布线板包括用于向电子电路元件供电的多个平面电源线。 平面电力线包括用于以预定电压向电子电路元件供电的一对平面电源线。 电子电路装置还包括布置在布线板上的多个位置处的多个阻尼元件。 阻尼元件在一对平面电源线的多个位置处连接在一对平面电源线之间。 阻尼元件降低了电源系统的阻抗，并阻止了电源线路系统的共振，从而减少了由电源线路系统引起的电源电压波动和由电源电压波动引起的噪声。