公开(公告)号：US07354867B2

公开(公告)日：2008-04-08

申请号：US10906112

申请日：2005-02-03

申请人： Scott D. Allen ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

发明人： Scott D. Allen ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

IPC分类号： H01L21/44 ,  H01L21/461

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device.

摘要翻译： 本发明的实施例通常涉及蚀刻工艺，更具体地涉及用于提高硅化镍上的电介质触点的产量的蚀刻处理。 在蚀刻过程中使用无氧原料气，以减少或消除在接触表面处的残余物，包括硅化物层的氧化和消耗。 接触表面的接触电阻降低，从而提高器件的性能。

公开(公告)号：US20090008785A1

公开(公告)日：2009-01-08

申请号：US12027407

申请日：2008-02-07

申请人： Scott D. ALLEN ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

发明人： Scott D. ALLEN ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

IPC分类号： H01L23/48

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device

摘要翻译： 本发明的实施例通常涉及蚀刻工艺，更具体地涉及用于提高硅化镍上的电介质触点的产量的蚀刻处理。 在蚀刻过程中使用无氧原料气，以减少或消除在接触表面处的残余物，包括硅化物层的氧化和消耗。 接触表面的接触电阻降低，从而提高器件的性能

公开(公告)号：US07060626B2

公开(公告)日：2006-06-13

申请号：US10604087

申请日：2003-06-25

申请人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

发明人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144

摘要： A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

摘要翻译： 一种用于形成半导体晶片的方法，包括将第一图案化抗蚀剂施加到晶片的至少一个第一预定区域，其中所述晶片的所述至少一个第一预定区域被所述第一图案化抗蚀剂保护并且所述晶片的第一剩余部分 不受所述第一图案化抗蚀剂的保护; 蚀刻所述晶片的未被所述第一图案抗蚀剂保护的所述第一剩余部分; 从所述晶片剥离第一图案抗蚀剂; 将第二图案化抗蚀剂施加到所述晶片的至少一个第二预定区域，其中所述晶片的所述至少一个第二预定区域被第二图案化抗蚀剂保护，并且第二剩余部分不被所述第二图案化抗蚀剂保护; 蚀刻不被所述第二图案化抗蚀剂保护的所述第二剩余部分; 以及从所述晶片剥离所述第二图案化抗蚀剂。

公开(公告)号：US06576507B1

公开(公告)日：2003-06-10

申请号：US09712510

申请日：2000-11-14

申请人： Kenneth A. Bandy ,  Stuart D. Cheney ,  Gary L. Milo ,  Yutong Wu

发明人： Kenneth A. Bandy ,  Stuart D. Cheney ,  Gary L. Milo ,  Yutong Wu

IPC分类号： H01L218249

CPC分类号： H01L21/8249

摘要： The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer 26 is deposited on the raised and recessed regions 28 of the semiconductor substrate 10. A selectively removable filler layer 30 is then deposited on the FET protection layer 26 with a thickness to over-fill the recessed regions 28 of the gates 24 of the FETs. The selectively removable filler layer 30 is then planarized until the FET protection layer 26 on top of the gates 24 is exposed. The recessed regions 28 between the gates 24 are left substantially filled with selectively removable filler layer 30. The selectively removable filler layer 30 in the region where the BJT is formed is patterned and an opening 32 is made to allow for the depositing of layers of different materials 34, 36, 38, 40, 42, 44 used in the construction of the BJT. The layer of different materials 34, 36, 38, 40, 42, 44 are processed by methods known in the art to form polysilicon emitter 46 of the BJT. Due to selectively removable filler layer 30 creating a substantially planar surface in the recessed regions 28 of the FETs, little to none of the layers of different materials 34, 36, 38, 40, 42, 44 that are used in the construction of the BJT are deposited within the recessed regions 28. Thus, removal of the layers of different materials 34, 36, 38, 40 (40′), 42, 44 from the FET region is simplified. After removal of the layers of different materials 34, 36, 38, 40 (40′), 42, 44 from the FET region, the selectively removable filler layer 30 is removed selectively to the FET protection layer 26. The FET protection layer 26 is then removed. The recessed regions 28 between the gates 24 of the FETs are free from residual films.

摘要翻译： 本发明旨在用于在FET之后形成BJT的BiCMOS技术。 薄的FET保护层26沉积在半导体衬底10的凸起和凹陷区域28上。然后，可选择地移除的填充层30沉积在FET保护层26上，其厚度足以使栅极的凹陷区域28过度填充 24个FET。 然后可选择性地移除的填充层30被平坦化，直到露出栅极24顶部的FET保护层26为止。 门24之间的凹陷区域28基本上被可选择地移除的填充层30填充。形成BJT的区域中的可选择性地移除的填充层30被图案化并且形成开口32以允许沉积不同的层 用于建造BJT的材料34,36,38,40,42,44。 通过本领域已知的方法来处理不同材料层34,36,38,40,42,44的层以形成BJT的多晶硅发射器46。 由于选择性地可移除的填充层30在FET的凹陷区域28中产生基本平坦的表面，所以在BJT的构造中使用的不同材料34,36,38,40,42,44的层几乎不下降 沉积在凹陷区域28内。因此，从FET区域去除不同材料层34,36,38,40（40'），42,44的层被简化。 在从FET区域去除不同材料34,36,38,40（40'），42,44的层之后，可选择地移除的填充层30被选择性地去除到FET保护层26.FET保护层26是 然后删除。 FET的栅极24之间的凹陷区域28没有残留的膜。