公开(公告)号：US20110029738A1

公开(公告)日：2011-02-03

申请号：US12902045

申请日：2010-10-11

申请人： Scott Douglas Clark ,  Andrew Henry Wottreng

发明人： Scott Douglas Clark ,  Andrew Henry Wottreng

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F2212/1016

摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

摘要翻译： 本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。

公开(公告)号：US07814279B2

公开(公告)日：2010-10-12

申请号：US11388013

申请日：2006-03-23

申请人： Scott Douglas Clark ,  Andrew Henry Wottreng

发明人： Scott Douglas Clark ,  Andrew Henry Wottreng

IPC分类号： G06F13/00 ,  G06F12/08

CPC分类号： G06F12/0817 ,  G06F2212/1016

摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

摘要翻译： 本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。

公开(公告)号：US07530068B2

公开(公告)日：2009-05-05

申请号：US10738720

申请日：2003-12-17

申请人： Scott Douglas Clark ,  Michael Norman Day ,  Charles Ray Johns ,  Andrew Henry Wottreng

发明人： Scott Douglas Clark ,  Michael Norman Day ,  Charles Ray Johns ,  Andrew Henry Wottreng

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/5011

摘要： A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.

摘要翻译： 提供用于有效地管理有限资源的方法和装置是给定的计算机系统。 该系统利用令牌管理器，将令牌分配给相关联的请求者的组。 然后请求者利用令牌来占用给定的资源。 因此，这些令牌的分配可以防止由于缺乏可用资源而导致拒绝服务的问题。

公开(公告)号：US08103835B2

公开(公告)日：2012-01-24

申请号：US12902045

申请日：2010-10-11

申请人： Scott Douglas Clark ,  Andrew Henry Wottreng

发明人： Scott Douglas Clark ,  Andrew Henry Wottreng

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0817 ,  G06F2212/1016

摘要： Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

摘要翻译： 本发明的实施例提供了通过保持加速器和CPU之间的一致性来减少节点间带宽消耗的方法和系统。 CPU和加速器可以聚集在多处理环境中的单独的节点上。 包含共享存储器设备的每个节点可以维护目录以跟踪可能在其他节点处被缓存的共享存储器的块。 因此，只有当存储器位置已被缓存在节点外部时，命令和地址才可以发送到其他节点上的处理器和加速器。 另外，因为加速器通常不能访问与CPU相同的数据，所以只能将初始读，写和同步操作传输到其他节点。 对数据的中间访问可以非相干地执行。 结果，可以减少用于维持一致性所消耗的芯片间带宽。

公开(公告)号：US06567839B1

公开(公告)日：2003-05-20

申请号：US08957002

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a thread switch manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储可以发生线程切换的条件。 在发生线程切换事件时，动态询问所有线程的状态和优先级，以确定哪个线程应该是执行处理器的主动线程。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程开关逻辑还响应于能够改变不同线程的优先级并因此取代线程切换事件的线程切换管理器。

公开(公告)号：US6076157A

公开(公告)日：2000-06-13

申请号：US956577

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/44 ,  G06F9/24

CPC分类号： G06F9/4825 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US20120284465A1

公开(公告)日：2012-11-08

申请号：US13549898

申请日：2012-07-16

申请人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

发明人： Bradly George Frey ,  Michal Ostrowski ,  Andrew Henry Wottreng

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F9/45558 ,  G06F2009/45583

摘要： An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.

公开(公告)号：US06212544B1

公开(公告)日：2001-04-03

申请号：US08958718

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  William Thomas Flynn ,  Andrew Henry Wottreng

IPC分类号： G06F946

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程切换控制寄存器，用于存储发生线程切换的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程切换逻辑还具有前向进度计数寄存器，以防止多线程处理器中的线程之间的重复无效线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US6105051A

公开(公告)日：2000-08-15

申请号：US956875

申请日：1997-10-23

申请人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

发明人： John Michael Borkenhagen ,  Richard James Eickemeyer ,  William Thomas Flynn ,  Steven R. Kunkel ,  Sheldon Bernard Levenstein ,  Andrew Henry Wottreng

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3851

摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

摘要翻译： 用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。 多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。 每个线程根据执行状态在线程状态寄存器中具有相应的状态。 线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。 线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。 线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。 线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

公开(公告)号：US20090144452A1

公开(公告)日：2009-06-04

申请号：US12275241

申请日：2008-11-21

申请人： Kerry Christopher Imming ,  John David Irish ,  Tolga Ozguner ,  Andrew Henry Wottreng

发明人： Kerry Christopher Imming ,  John David Irish ,  Tolga Ozguner ,  Andrew Henry Wottreng

IPC分类号： G06F15/16 ,  H04Q11/00

CPC分类号： H04L69/22

摘要： A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.

摘要翻译： 提供了一种方法，装置和计算机程序产品，用于基于发送端口实现条件分组改变。 提供了一种用于实现数据包更改的选择机制。 与所发送的分组相关联的帧改变指令和发送端口号的序列被应用于选择机制。 选择机制响应于应用的帧改变​​指令序列和与分组相关联的端口号，对发送的分组进行改变。 选择机制包括：多路复用器，其依次接收与正在发送的分组相关联的帧改变指令和端口号;以及间接数据阵列，用于从间接数据阵列提供分组改变数据。