利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

207 条记录 (耗时 0.058 秒)

    System and method for conditional task switching during ordering scope transitions
    9.
    发明授权
    System and method for conditional task switching during ordering scope transitions 有权
    在订购范围转换期间进行条件任务切换的系统和方法

    公开(公告)号：US09372724B2

    公开(公告)日：2016-06-21

    申请号：US14231789

    申请日：2014-04-01

    申请人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

    发明人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

    IPC分类号： G06F9/48

    CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/48

    摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

    摘要翻译： 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 硬件模块在订购范围管理器的第一存储位置处存储第一订购范围标识符。 第一个订购范围标识符指示第一个任务正在操作的第一个订购范围。订购范围管理器增加第一个订购范围标识符以创建新的订购范围标识符。 响应于确定处理器核被授权将第一任务从第一排序范围转换到与新排序范围标识符相关联的第二排序范围，订购范围管理器向处理器核提供提示信息。 处理器核心从第一订购范围转换到第二订购范围，而不响应于提示信息完成任务切换。

    Event triggered memory mapped access
    10.
    发明授权
    Event triggered memory mapped access 有权
    事件触发内存映射访问

    公开(公告)号：US08700878B2

    公开(公告)日：2014-04-15

    申请号：US12485190

    申请日：2009-06-16

    申请人： William D. Schwarz ,  Joseph P. Gergen ,  Jason T. Nearing ,  Zheng Xu

    发明人： William D. Schwarz ,  Joseph P. Gergen ,  Jason T. Nearing ,  Zheng Xu

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0292 ,  G06F11/3636

    摘要： In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.

    摘要翻译： 在一个或多个实施例中，数据处理系统可以包括能够执行指令集架构的指令的至少一个核心以及耦合到所述至少一个核心的触发的存储器映射访问（tMMA）系统。 tMMA系统可以接收一个或多个事件，并作为响应执行一个或多个动作。 例如，动作可以包括可以包括对存储器映射的地址的写入，从存储器映射的地址的读取，随后写入存储器映射的两个相应地址的读取的事务，和/或 提取事务。 事务的结果（例如，数据读取，数据写入，错误等）可用于生成跟踪消息。 例如，tMMA系统可以生成包含事务结果的跟踪消息，并将跟踪消息发送到跟踪消息总线。