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公开(公告)号：US06834022B2
公开(公告)日：2004-12-21
申请号：US10717862
申请日：2003-11-18
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.
摘要翻译： 存储器件包括地址选择电路，用于存储存储器单元的选定行的地址。 在刷新模式下，只刷新所选行的存储单元。 所选择的行的地址可以在存储器操作模式期间由存储器设备自动存储，或者在编程模式期间由用户手动存储。
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公开(公告)号：US06650587B2
公开(公告)日：2003-11-18
申请号：US09988988
申请日：2001-11-19
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.
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3.发明授权Apparatus and method for disabling and re-enabling access to IC test functions 有权用于禁用和重新启用IC测试功能的设备和方法公开(公告)号：US06255838B1
公开(公告)日：2001-07-03
申请号：US09567796
申请日：2000-05-09
IPC分类号： G01R3128
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。
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4.发明授权公开(公告)号：US06255837B1
公开(公告)日：2001-07-03
申请号：US09567632
申请日：2000-05-09
IPC分类号： G01R3128
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the sane or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备处检测到合格或其他信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。
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公开(公告)号：US06130834A
公开(公告)日：2000-10-10
申请号：US274932
申请日：1999-03-23
CPC分类号： G11C17/18
摘要： Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.
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公开(公告)号：US5721703A
公开(公告)日：1998-02-24
申请号：US641114
申请日：1996-04-29
CPC分类号： G11C7/1045 , G11C16/20
摘要： An integrated circuit package includes an integrated circuit device that operates in more than one operational mode. The operational mode of the integrated circuit device is controlled by a mode select input. Examples of operational modes include fast page and block modes, two- and three-latency modes, and normal and test modes. A reprogrammable mode select circuit within the integrated circuit package produces a mode control signal that drives a mode select input of the integrated circuit device. The operational mode of the integrated circuit device then corresponds to the state of the mode select signal.
摘要翻译： 集成电路封装包括以多于一种操作模式操作的集成电路器件。 集成电路器件的工作模式由模式选择输入控制。 操作模式的示例包括快速页面和块模式，两种和三种延迟模式，以及正常和测试模式。 集成电路封装内的可再编程模式选择电路产生驱动集成电路器件的模式选择输入的模式控制信号。 然后，集成电路装置的工作模式对应于模式选择信号的状态。
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公开(公告)号：US06826071B2
公开(公告)日：2004-11-30
申请号：US10098262
申请日：2002-03-15
IPC分类号： G11C1700
CPC分类号： G11C17/18
摘要： A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory. The method includes the steps of: connecting the antifuse in series with a node; providing current to the node through a parallel combination of a first transistor and a second transistor that is sufficient to charge the node from a first voltage to a second voltage; and detecting whether the voltage at the node charges to the second voltage or remains at the first voltage to indicate that the antifuse is programmed properly; outputting first and second signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is programmed properly.
摘要翻译： 验证半导体存储器中未编程的反熔丝是否泄漏的方法。 该方法包括以下步骤：将反熔丝与节点串联连接; 向节点提供电流，电流足以使节点从第一电压到第二电压充电; 检测节点处的电压是否充电到第二电压，或者保持在第一电压以指示反熔丝泄漏; 输出指示检测结果的信号; 并且检测节点处的电压保持在第一电压，表示反熔丝泄漏。 在另一个实施例中，验证在半导体存储器中是否正确地编程了反熔丝的方法。 该方法包括以下步骤：将反熔丝与节点串联连接; 通过第一晶体管和第二晶体管的并联组合向节点提供电流，其足以将节点从第一电压充电到第二电压; 并且检测节点处的电压是否充电到第二电压或者保持在第一电压以指示反熔丝被正确编程; 输出表示检测结果的第一和第二信号; 并且检测节点处的电压保持在第一电压，表示反熔丝被正确编程。
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公开(公告)号：US06590407B2
公开(公告)日：2003-07-08
申请号：US10222113
申请日：2002-08-16
IPC分类号： G01R3128
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。
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公开(公告)号：US06903991B2
公开(公告)日：2005-06-07
申请号：US10178605
申请日：2002-06-24
IPC分类号： G01F1/66 , G01F1/684 , G01F1/696 , G01F1/86 , G01F5/00 , G01F25/00 , G11C17/00 , G11C17/16 , G11C17/18 , G11C7/00
摘要： Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.
摘要翻译： 提供用于编程反熔丝元件的电路，其允许同时对一个组中的所有反熔丝元件进行编程，从而提高可以对反熔丝元件进行编程的速度。 在一个实施例中，反馈电路与每个反熔丝元件相关联，以便在程序设计之后停止通过反熔丝元件的电流流动。 在另一个实施例中，提供电路用于为每个用于编程的反熔丝元件产生单独的编程脉冲。
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公开(公告)号：US06646459B2
公开(公告)日：2003-11-11
申请号：US09813130
申请日：2001-03-19
IPC分类号： G01R3128
CPC分类号： G01R31/31701 , G01R31/2884
摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.
摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。
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