公开(公告)号：US20170365612A1

公开(公告)日：2017-12-21

申请号：US15692606

申请日：2017-08-31

申请人： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik Moon ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

发明人： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik Moon ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

IPC分类号： H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522

CPC分类号： H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US20170133389A1

公开(公告)日：2017-05-11

申请号：US15217313

申请日：2016-07-22

申请人： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik MOON ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

发明人： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik MOON ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US20170069636A1

公开(公告)日：2017-03-09

申请号：US15160335

申请日：2016-05-20

申请人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

发明人： Se-Jun PARK ,  Jang-Gn Yun ,  Sung-Min Hwang ,  Ahn-Sik Moon ,  Zhiliang Xia

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

摘要翻译： 一种半导体器件包括多个绝缘图案和多个栅极交替重复堆叠在基板上，沟道图案沿基本上垂直于基板顶表面的第一方向延伸穿过栅极，沟道图案 和衬底，以及沟道图案和半导体图案之间的导电图案。 导电图案将沟道图案电连接到半导体图案。 导电图案接触通道图案的底部边缘和半导体图案的上表面。