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    VERTICAL MEMORY DEVICES
    3.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20180247950A1

    公开(公告)日：2018-08-30

    申请号：US15801551

    申请日：2017-11-02

    申请人： Su-Ok YUN ,  Jang-Gn YUN ,  Joon-Sung LIM ,  Sung-Min HWANG

    发明人： Su-Ok YUN ,  Jang-Gn YUN ,  Joon-Sung LIM ,  Sung-Min HWANG

    IPC分类号： H01L27/11556 ,  H01L27/11582

    CPC分类号： H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.

    Semiconductor Devices and Methods for Forming the Same
    4.
    发明申请
    Semiconductor Devices and Methods for Forming the Same 审中-公开

    公开(公告)号：US20170323901A1

    公开(公告)日：2017-11-09

    申请号：US15661718

    申请日：2017-07-27

    申请人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    发明人： Jang-Gn Yun ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    IPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

    SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME 有权
    半导体器件及其形成方法

    公开(公告)号：US20160225714A1

    公开(公告)日：2016-08-04

    申请号：US14974567

    申请日：2015-12-18

    申请人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    发明人： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

    IPC分类号： H01L23/528 ,  H01L27/115 ,  H01L23/522

    CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

    摘要： A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

    摘要翻译： 半导体器件可以包括延伸到台阶区域的单元阵列区域中的单元栅极导电图案，延伸穿过单元栅极导电图案的单元阵列区域中的单元垂直结构，单元栅极导电上的单元栅极接触结构 在步进区域中的图案，单元栅极导电图案中的单元栅极接触区域并与单元栅极接触结构对准，与单元栅极导电图案间隔开的第一外围接触结构，与第一外部接触结构间隔开的第二外部接触结构 周边接触结构，第一周边接触结构下面的第一周边接触区域和第二周边接触结构下面的第二周边接触区域。 单元栅极接触区域可以包括第一元件，并且单元栅极导电图案的其余部分可以基本上不包括第一元件。

    SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20160163732A1

    公开(公告)日：2016-06-09

    申请号：US14962263

    申请日：2015-12-08

    申请人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

    发明人： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

    IPC分类号： H01L27/115 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

    摘要翻译： 提供了制造半导体器件的半导体器件和方法。 半导体器件可以包括在半导体衬底上包括开口的半导体图案。 外围晶体管和外围互连结构可以设置在半导体衬底和半导体图案之间。 外围互连结构可以电连接到外围晶体管。 单元栅极导电图案可以设置在半导体图案上。 单元垂直结构可以延伸穿过单元栅极导电图案并且可以连接到半导体图案。 单元位线接触插头可以设置在单元垂直结构上。 位线可以设置在单元位线接触插头上。 外围位线接触结构可以设置在位线和外围互连结构之间。 外围位线接触结构可延伸穿过半导体的开口。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING DOUBLE SPACERS ON SIDEWALL OF FLATING GATE, ELECTRONIC DEVICE INCLUDING THE SAME 有权
    半导体存储器件，其中包括在平板门，包括它们的电子器件上的双重间隔

    公开(公告)号：US20090096005A1

    公开(公告)日：2009-04-16

    申请号：US12133587

    申请日：2008-06-05

    申请人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    发明人： Joon-Sung LIM ,  Jong-Ho PARK ,  Hyun-Chul BACK ,  Sung-Hun LEE

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.

    摘要翻译： 半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。 浮动门设置在活动区域​​上。 控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。 控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。 第一间隔件设置在相邻浮动门的侧壁上。 每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。 第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。 还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。