公开(公告)号：US09059704B2

公开(公告)日：2015-06-16

申请号：US13477192

申请日：2012-05-22

申请人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

发明人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

IPC分类号： G06F1/00 ,  H03K19/177 ,  H03K19/173 ,  G06F3/06

CPC分类号： H03K19/173 ,  G06F1/3243 ,  G06F3/0679 ,  H03K19/17772 ,  Y02D10/152

摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

摘要翻译： 目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。 可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。 在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

公开(公告)号：US08570065B2

公开(公告)日：2013-10-29

申请号：US13437961

申请日：2012-04-03

申请人： Hidetomo Kobayashi ,  Masami Endo ,  Yutaka Shionoiri ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Kazuaki Ohshima ,  Seiichi Yoneda ,  Jun Koyama

发明人： Hidetomo Kobayashi ,  Masami Endo ,  Yutaka Shionoiri ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Kazuaki Ohshima ,  Seiichi Yoneda ,  Jun Koyama

IPC分类号： H03K19/177 ,  G11C11/24

CPC分类号： H03K19/17796 ,  G11C16/0433 ,  H01L27/11803 ,  H01L27/1203

摘要： A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.

摘要翻译： 提供了可以执行动态配置的低功耗可编程LSI。 可编程LSI包括多个逻辑元件。 多个逻辑元件各自包括配置存储器。 多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。 配置存储器包括一组易失性存储电路和非易失性存储电路。 非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管和一对电极中的一个电极与晶体管截止时被设置为浮置状态的节点电连接的电容器。

公开(公告)号：US20120311365A1

公开(公告)日：2012-12-06

申请号：US13477192

申请日：2012-05-22

申请人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

发明人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

IPC分类号： G06F1/32

CPC分类号： H03K19/173 ,  G06F1/3243 ,  G06F3/0679 ,  H03K19/17772 ,  Y02D10/152

摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

摘要翻译： 目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。 可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。 在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

公开(公告)号：US08824194B2

公开(公告)日：2014-09-02

申请号：US13472741

申请日：2012-05-16

申请人： Hidetomo Kobayashi ,  Yutaka Shionoiri ,  Tatsuji Nishijima

发明人： Hidetomo Kobayashi ,  Yutaka Shionoiri ,  Tatsuji Nishijima

IPC分类号： G11C11/24

CPC分类号： H01L27/1225 ,  G06F9/3804 ,  G06F9/3814 ,  G11C11/404 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1156 ,  H01L27/1255

摘要： In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to be wrong. Note that the arithmetic portion controls transmission and reception of the instruction between the flip-flop and the memory which are included in the reading portion. This enables elimination of redundant operations in the reading portion in the case where an instruction read by the reading portion after the branch prediction turns out to be wrong is a subroutine, or the like. That is, the instruction held in the memory is transmitted back to the flip-flop without rereading of the same instruction by the reading portion, whereby the instruction can be output to the arithmetic portion.

摘要翻译： 在利用读取指令的读取部分执行流水线处理的半导体器件和执行根据该指令的操作的算术部分中，当分支预测时，保持在读取部分中的指令从触发器发送到存储器 原来是错的。 注意，算术部分控制包括在读取部分中的触发器和存储器之间的指令的发送和接收。 在分支预测结果为错误的读取部读出的指示是子程序等的情况下，能够消除读取部中的冗余动作。 也就是说，保持在存储器中的指令被发送回到触发器，而不用读取部分重新读取相同的指令，从而可以将该指令输出到算术部分。

公开(公告)号：US08540161B2

公开(公告)日：2013-09-24

申请号：US13187777

申请日：2011-07-21

申请人： Yutaka Shionoiri ,  Tatsuji Nishijima ,  Misako Sato ,  Shuhei Maeda

发明人： Yutaka Shionoiri ,  Tatsuji Nishijima ,  Misako Sato ,  Shuhei Maeda

IPC分类号： G06K19/06

CPC分类号： H01L27/13 ,  G06K19/07783 ,  H01L23/645 ,  H01L27/1225 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of this invention is to provide a semiconductor device (an RFID) with reduced loss of voltage/current corresponding to a threshold value of a transistor, and having a voltage/current rectification property. Another object of this invention is to simplify a fabrication process and a circuit configuration. A rectifier circuit is provided in an element included in a semiconductor device (RFID) capable of communicating data wirelessly. As compared to the case where only a diode is provided, coils are provided between gate terminals and drain terminals of transistors constituting the diode in a rectifier circuit, so that the coils overlap an antenna which receives a radio wave, whereby a voltage output by the rectifier circuit is increased using electromagnetic coupling between the antenna which receives a radio wave and the coils, so that the rectification efficiency is improved.

摘要翻译： 本发明的目的是提供一种具有与晶体管的阈值相对应的具有降低的电压/电流损耗并且具有电压/电流整流特性的半导体器件（RFID）。 本发明的另一个目的是简化制造过程和电路结构。 整流电路设置在能够无线通信数据的半导体器件（RFID）中的元件中。 与仅提供二极管的情况相比，在整流电路中在构成二极管的晶体管的栅极端子和漏极端子之间设置线圈，使得线圈与接收无线电波的天线重叠，由此由 使用接收无线电波的天线与线圈之间的电磁耦合来提高整流电路，从而提高整流效率。

公开(公告)号：US08207756B2

公开(公告)日：2012-06-26

申请号：US12912397

申请日：2010-10-26

申请人： Yutaka Shionoiri ,  Hidetomo Kobayashi

发明人： Yutaka Shionoiri ,  Hidetomo Kobayashi

IPC分类号： H03K19/096

CPC分类号： H01L29/7869 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/0375 ,  H03K19/0016 ,  H03K19/096

摘要： In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

摘要翻译： 在执行时钟门控的逻辑电路中，待机功率降低或故障被抑制。 该逻辑电路包括在不提供时钟信号的时段内处于源极端子和漏极端子之间存在电位差的关断状态的晶体管。 使用其中氢浓度降低的氧化物半导体形成晶体管的沟道形成区域。 具体地说，氧化物半导体的氢浓度为5×1019（原子/ cm3）以下。 因此，可以减小晶体管的漏电流。 结果，在逻辑电路中，可以实现待机功率的降低和故障的抑制。

公开(公告)号：US20090079572A1

公开(公告)日：2009-03-26

申请号：US11919497

申请日：2006-05-17

申请人： Tomoaki Atsumi ,  Yutaka Shionoiri ,  Hidetomo Kobayashi

发明人： Tomoaki Atsumi ,  Yutaka Shionoiri ,  Hidetomo Kobayashi

IPC分类号： G08B13/22

CPC分类号： G06K19/07749 ,  G06K19/0708

摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。

公开(公告)号：US09117701B2

公开(公告)日：2015-08-25

申请号：US13459537

申请日：2012-04-30

申请人： Hiroyuki Tomatsu ,  Hidetomo Kobayashi ,  Yutaka Shionoiri

发明人： Hiroyuki Tomatsu ,  Hidetomo Kobayashi ,  Yutaka Shionoiri

IPC分类号： G11C11/00 ,  G11C7/00 ,  H01L27/115 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： H01L27/1156 ,  G11C7/02 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

摘要： Noise generated on a word line is reduced without increasing a load on the word line. A semiconductor device is provided in which a plurality of storage elements each including at least one switching element are provided in matrix; each of the plurality of storage elements is electrically connected to a word line and a bit line; the word line is connected to a gate (or a source and a drain) of a transistor in which minority carriers do not exist substantially; and capacitance of the transistor in which minority carriers do not exist substantially can be controlled by controlling a potential of a source and a drain (or a gate) the transistor in which minority carriers do not exist substantially. The transistor in which minority carriers do not exist substantially may include a wide band gap semiconductor.

摘要翻译： 在字线上产生的噪声减小，而不增加字线上的负载。 提供一种半导体器件，其中包括至少一个开关元件的多个存储元件设置为矩阵; 多个存储元件中的每一个电连接到字线和位线; 字线连接到其中少数载体基本不存在的晶体管的栅极（或源极和漏极）; 并且通过控制其中不存在少数载流子的晶体管的源极和漏极（或栅极）的电位，可以控制其中不存在少数载流子的晶体管的电容。 少数载流子不存在的晶体管可以包括宽带隙半导体。

公开(公告)号：US08937304B2

公开(公告)日：2015-01-20

申请号：US13356828

申请日：2012-01-24

申请人： Masashi Fujita ,  Yutaka Shionoiri ,  Hiroyuki Tomatsu ,  Hidetomo Kobayashi

发明人： Masashi Fujita ,  Yutaka Shionoiri ,  Hiroyuki Tomatsu ,  Hidetomo Kobayashi

IPC分类号： H01L27/108 ,  G11C11/34 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12

CPC分类号： H01L27/1225 ,  H01L21/84 ,  H01L27/088 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1222 ,  H01L27/1251

摘要： A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

摘要翻译： 提供在绝缘区域上方设置有在第一半导体区域和第二半导体区域上设置绝缘区域的衬底上的第一场效应晶体管; 设置在所述基板上的绝缘层; 第二场效应晶体管，其设置在所述绝缘层的一个平面上，并且包括氧化物半导体层; 并提供控制终端。 控制端子以与第二场效应晶体管的源极和漏极相同的步骤形成，并且用于控制第一场效应晶体管的阈值电压的电压被提供给控制端子。

公开(公告)号：US08837203B2

公开(公告)日：2014-09-16

申请号：US13467490

申请日：2012-05-09

申请人： Yutaka Shionoiri ,  Hidetomo Kobayashi

发明人： Yutaka Shionoiri ,  Hidetomo Kobayashi

IPC分类号： G11C11/24 ,  H01L27/105 ,  H01L21/84 ,  H01L27/12 ,  G11C11/00 ,  H01L27/115 ,  H01L27/108

CPC分类号： G11C11/24 ,  G11C11/005 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

摘要翻译： 即使在非常短的时间断电或电源电压下降（例如断电或下垂）的情况下，易失性存储器中的数据也可能传统上会丢失。 鉴于上述情况，目的是即使使用用于高速数据处理的易失性存储器来延长数据保持时间。 数据保留时间可以通过备份存储在包括电容器和氧化物半导体晶体管的存储器中的易失性存储器中的数据内容来扩展。