公开(公告)号：US20230073330A1

公开(公告)日：2023-03-09

申请号：US18056304

申请日：2022-11-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Hui Min LER ,  Soon Wei WANG ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

公开(公告)号：US20240266264A1

公开(公告)日：2024-08-08

申请号：US18165545

申请日：2023-02-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Hui Min LER ,  Swee Har KHOR ,  Ziming CHANG ,  Kok Yang LAU ,  Heng Giap ONG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49582 ,  H01L21/561 ,  H01L24/96 ,  H01L2224/95001 ,  H01L2224/96

Abstract: Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package.

公开(公告)号：US20250022831A1

公开(公告)日：2025-01-16

申请号：US18625487

申请日：2024-04-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Nam Khong THEN ,  Hui Min LER ,  Phillip CELAYA ,  Chee Hiong CHEW

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/495 ,  H01L25/065

Abstract: Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.

公开(公告)号：US20220208658A1

公开(公告)日：2022-06-30

申请号：US17136136

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Hui Min LER ,  Soon Wei WANG ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

公开(公告)号：US20200312749A1

公开(公告)日：2020-10-01

申请号：US16903706

申请日：2020-06-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Swee Har KHOR ,  Tian Hing LIM ,  Hui Min LER ,  Chee Hiong CHEW ,  Phillip CELAYA

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/00 ,  H01L23/60

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

公开(公告)号：US20250118635A1

公开(公告)日：2025-04-10

申请号：US18984351

申请日：2024-12-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Hui Min LER ,  Soon Wei WANG ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

公开(公告)号：US20230073773A1

公开(公告)日：2023-03-09

申请号：US18056100

申请日：2022-11-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Hui Min LER ,  Soon Wei WANG ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

公开(公告)号：US20180090421A1

公开(公告)日：2018-03-29

申请号：US15278203

申请日：2016-09-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Nam Khong THEN ,  Hui Min LER ,  Phillip CELAYA ,  Chee Hiong CHEW

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4853 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221

Abstract: A method for plating package leads, in some embodiments, comprises: providing a package having a lead electrically coupled to a tie bar; singulating said lead; electroplating said singulated lead using the tie bar; and singulating said tie bar.

公开(公告)号：US20170062310A1

公开(公告)日：2017-03-02

申请号：US14842571

申请日：2015-09-01

Applicant: Semiconductor Components Industries, LLC

Inventor： Swee Har KHOR ,  Tian Hing LIM ,  Hui Min LER ,  Chee Hiong CHEW ,  Phillip CELAYA

IPC: H01L23/495 ,  H01L23/00

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract translation: 在一个实施例中，公开了制造半导体器件的方法。