公开(公告)号：US20240282668A1

公开(公告)日：2024-08-22

申请号：US18172904

申请日：2023-02-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4334 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107

Abstract: A protective dam can relieve stress in a chip assembly of a high-power semiconductor device module used in electric vehicle or industrial applications. Some chip assemblies that incorporate copper spacers for thermal dissipation can cause the device module to become vulnerable to cracking. Adding a protective dam can absorb stress to prevent damage to materials surrounding the chip assembly. Various types of protective dams are presented, including high profile flexible protective dams, low profile flexible protective dams, metallic protective dams, and integral protective dams. The protective dams can be incorporated into a high-power semiconductor device module that features single sided or dual sided cooling via direct bond metal structures.

公开(公告)号：US20220415766A1

公开(公告)日：2022-12-29

申请号：US17929884

申请日：2022-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20220246434A1

公开(公告)日：2022-08-04

申请号：US17660477

申请日：2022-04-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

公开(公告)号：US20220159853A1

公开(公告)日：2022-05-19

申请号：US17588660

申请日：2022-01-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Yushuang YAO ,  Chee Hiong CHEW

IPC: H05K5/02 ,  H01L23/053 ,  H01L23/40

Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.

公开(公告)号：US20200344905A1

公开(公告)日：2020-10-29

申请号：US16587549

申请日：2019-09-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yushuang YAO

IPC: H05K5/06 ,  H05K7/20

Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.

公开(公告)号：US20200279747A1

公开(公告)日：2020-09-03

申请号：US16879378

申请日：2020-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20200258751A1

公开(公告)日：2020-08-13

申请号：US16861810

申请日：2020-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Eiji KUROSE ,  Chee Hiong CHEW ,  Soon Wei WANG

IPC: H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

公开(公告)号：US20200144200A1

公开(公告)日：2020-05-07

申请号：US16181876

申请日：2018-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino TOLENTINO ,  Chee Hiong CHEW ,  Yusheng LIN ,  Swee Har KHOR

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

公开(公告)号：US20200105648A1

公开(公告)日：2020-04-02

申请号：US16145517

申请日：2018-09-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yushuang YAO

IPC: H01L23/495 ,  H01L23/00

Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.

公开(公告)号：US20190252275A1

公开(公告)日：2019-08-15

申请号：US16396904

申请日：2019-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/055 ,  H01L23/498 ,  H01L23/053 ,  H01L25/07 ,  H01L23/04 ,  H01L23/492 ,  H01L21/50 ,  H01L23/00 ,  H01R4/48 ,  H01L23/50 ,  H01L23/10 ,  H01L23/057

CPC classification number: H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.