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    ULTRA-THIN MULTICHIP POWER DEVICES
    2.
    发明申请
    ULTRA-THIN MULTICHIP POWER DEVICES 有权

    公开(公告)号：US20210183799A1

    公开(公告)日：2021-06-17

    申请号：US17249154

    申请日：2021-02-22

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Nurul Nadiah MANAP ,  Shutesh KRISHNAN ,  Soon Wei WANG

    IPC: H01L23/00 ,  H01L25/065

    Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.

    QUAD FLAT NO LEADS PACKAGE
    5.
    发明申请
    QUAD FLAT NO LEADS PACKAGE 审中-公开

    公开(公告)号：US20180040539A1

    公开(公告)日：2018-02-08

    申请号：US15230179

    申请日：2016-08-05

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Soon Wei WANG ,  How Kiat LIEW ,  Jose Felixminia PALAGUD, JR.

    IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48

    Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

    BACKMETAL REMOVAL METHODS
    6.
    发明申请
    BACKMETAL REMOVAL METHODS 有权

    公开(公告)号：US20220238342A1

    公开(公告)日：2022-07-28

    申请号：US17659068

    申请日：2022-04-13

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

    IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

    SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK AND RELATED METHODS
    7.
    发明申请
    SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK AND RELATED METHODS 有权

    公开(公告)号：US20220208658A1

    公开(公告)日：2022-06-30

    申请号：US17136136

    申请日：2020-12-29

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Hui Min LER ,  Soon Wei WANG ,  Chee Hiong CHEW

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

    Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

    CHIP-ON-LEAD SEMICONDUCTOR DEVICE PACKAGES WITH ELECTRICALLY ISOLATED SIGNAL LEADS
    9.
    发明申请
    CHIP-ON-LEAD SEMICONDUCTOR DEVICE PACKAGES WITH ELECTRICALLY ISOLATED SIGNAL LEADS 审中-公开

    公开(公告)号：US20200035586A1

    公开(公告)日：2020-01-30

    申请号：US16045275

    申请日：2018-07-25

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jin Yoong LIONG ,  Soon Wei WANG ,  How Kiat LIEW

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

    Abstract: In a general aspect, a chip-on-lead semiconductor device package can include a leadframe having a plurality of signal leads. The plurality of signal leads can include at least two signal leads each having a first face with a first surface area and, opposite the first face, a second face with a second surface area, the second faces of the at least two signal leads being exposed on a surface of the chip-on-lead device package. The plurality of signal lead can also include at least one signal lead having a first face with a third surface area and, opposite the first face of the at least one signal lead, a second face with the second surface area, the second face of the at least one signal lead being exposed on the surface of the chip-on-lead semiconductor device package.

    ULTRA-THIN MULTICHIP POWER DEVICES
    10.
    发明申请
    ULTRA-THIN MULTICHIP POWER DEVICES 审中-公开

    公开(公告)号：US20190304940A1

    公开(公告)日：2019-10-03

    申请号：US15939843

    申请日：2018-03-29

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Nurul Nadiah MANAP ,  Shutesh KRISHNAN ,  Soon Wei WANG

    IPC: H01L23/00 ,  H01L25/065

    Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.

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