公开(公告)号：US20250065776A1

公开(公告)日：2025-02-27

申请号：US18551561

申请日：2022-03-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi OSADA ,  Noboru INOUE ,  Haruki KATAGIRI ,  Yosuke TSUKAMOTO ,  Mayumi MIKAMI ,  Kazuki TANEMURA ,  Kousuke SASAKI

IPC: B60L58/22 ,  B60L50/60 ,  B60L58/12 ,  G07C5/00 ,  H01M10/42 ,  H01M50/209 ,  H01M50/211 ,  H01M50/213 ,  H02J7/00

Abstract: A system is provided with which data on the internal state of a storage battery such as SOC-OCV characteristics and FCC can be obtained with high accuracy and highly accurate estimation is possible even in the case of repeating charging and discharging for a long period. The storage battery management system includes a vehicle that includes a unit enabling data transmission and reception; the vehicle includes a storage battery, a balancing circuit electrically connected to the storage battery, and a vehicle control unit having a function of controlling the balancing circuit; the storage battery includes an assembled battery including a plurality of battery cells; the vehicle control unit has a function of selecting an estimated value that most closely shows a state of each of the battery cells included in the assembled battery; and the balancing circuit has a function of being controlled in accordance with the selected estimated value.

公开(公告)号：US20220262953A1

公开(公告)日：2022-08-18

申请号：US17628091

申请日：2020-07-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Takahiko ISHIZU ,  Takeshi AOKI ,  Masashi FUJITA ,  Kazuma FURUTANI ,  Kousuke SASAKI

IPC: H01L29/786 ,  H01L27/108 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G06F7/544

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20220321006A1

公开(公告)日：2022-10-06

申请号：US17621338

申请日：2020-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kousuke SASAKI ,  Yuto YAKUBO ,  Kei TAKAHASHI

IPC: H02M3/156 ,  H02H7/18 ,  H01L27/12 ,  H01L29/786

Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

公开(公告)号：US20240079583A1

公开(公告)日：2024-03-07

申请号：US18262126

申请日：2022-01-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya SHIMADA ,  Kousuke SASAKI ,  Takashi HIRAHARA ,  Yusuke YOSHITANI ,  Mayumi MIKAMI ,  Yohei MOMMA

IPC: H01M4/525 ,  C01G51/00

CPC classification number: H01M4/525 ,  C01G51/42 ,  C01P2002/60 ,  C01P2002/72 ,  C01P2004/03 ,  C01P2006/40 ,  H01M2004/028

Abstract: A novel method for forming a positive electrode active material is provided. The method for forming a positive electrode active material includes causing a reaction between a cobalt aqueous solution and an alkaline aqueous solution to form a cobalt compound; mixing the cobalt compound and a lithium compound and performing a first heat treatment to form a first composite oxide; mixing the first composite oxide and a compound containing a first additive element and performing a second heat treatment to form a second composite oxide; and mixing the second composite oxide and a compound containing a second additive element and performing a third heat treatment. The first heat treatment is performed at a temperature higher than or equal to 700° C. and lower than or equal to 1100° C. The second heat treatment is performed at a temperature higher than or equal to 700° C. and lower than or equal to 1000° C. The third heat treatment is performed at a temperature equal to the temperature of the second heat treatment or at a temperature lower than the temperature of the second heat treatment.

公开(公告)号：US20230337439A1

公开(公告)日：2023-10-19

申请号：US18028812

申请日：2021-10-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Kousuke SASAKI

IPC: H10B53/30 ,  H10B53/40 ,  G11C11/22

CPC classification number: H10B53/30 ,  H10B53/40 ,  G11C11/221 ,  G11C11/2273

Abstract: Provided is a semiconductor device capable of reading data with high accuracy. The semiconductor device includes first and second memory cells and a switch. The first memory cell includes first and second transistors and a first capacitor, and the second memory cell includes third and fourth transistors and a second capacitor. The first and second capacitors each include a ferroelectric layer between a pair of electrodes. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to one of the electrodes of the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and the gate of the fourth transistor is electrically connected to one of the electrodes of the second capacitor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor via the switch.