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    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE
    1.
    发明公开
    IMAGING DEVICE, OPERATION METHOD THEREOF, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240196117A1

    公开(公告)日：2024-06-13

    申请号：US18584020

    申请日：2024-02-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Seiichi YONEDA ,  Hiroki INOUE

    IPC: H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

    CPC classification number: H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

    Abstract: An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.

    Semiconductor Device and Driving Method Thereof
    2.
    发明申请
    Semiconductor Device and Driving Method Thereof 有权

    公开(公告)号：US20220416767A1

    公开(公告)日：2022-12-29

    申请号：US17779675

    申请日：2020-11-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Seiichi YONEDA ,  Yusuke NEGORO

    IPC: H03K3/011 ,  H01L27/146 ,  H03K17/56

    Abstract: A semiconductor device with a small circuit scale is provided. The semiconductor device includes a first circuit and a second circuit. The first circuit includes first to n-th (n is an integer of 2 or more) transistors and the second circuit includes (n+1)-th to 2n-th transistors. The first to n-th transistors are connected in parallel to each other and the (n+1)-th to 2n-th transistors are connected in series to each other. First to n-th signals are supplied to the first circuit and the second circuit. The first circuit has a function of outputting a first potential when each of potentials of the first to n-th signals is lower than or equal to a first reference potential, and outputting a second potential when at least one of the potentials of the first to n-th signals is higher than the first reference potential. The second circuit has a function of outputting a third potential when each of the potentials of the first to n-th signals is higher than a second reference potential, and outputting the first potential when at least one of the potentials of the first to n-th signals is lower than or equal to the second reference potential.

    IMAGING DEVICE
    3.
    发明申请
    IMAGING DEVICE 有权

    公开(公告)号：US20220077205A1

    公开(公告)日：2022-03-10

    申请号：US17517705

    申请日：2021-11-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Hiroki INOUE ,  Takuro OHMARU

    IPC: H01L27/146 ,  H01L21/8234 ,  H04N5/225 ,  H01L27/12 ,  H01L27/088 ,  H01L29/786 ,  H01L31/075

    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

    AMPLIFIER CIRCUIT, LATCH CIRCUIT, AND SENSING DEVICE
    4.
    发明申请
    AMPLIFIER CIRCUIT, LATCH CIRCUIT, AND SENSING DEVICE 有权

    公开(公告)号：US20210294367A1

    公开(公告)日：2021-09-23

    申请号：US17265361

    申请日：2019-07-29

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kei TAKAHASHI ,  Yuto YAKUBO ,  Hiroki INOUE

    IPC: G05F1/56 ,  H03F3/45 ,  H01L29/786 ,  H03K3/356

    Abstract: An output gain of a latch circuit is increased. The latch circuit includes a first circuit, a second circuit, and first to fourth transistors. The latch circuit includes a first input/output terminal and a second input/output terminal. The first circuit and the second circuit have a function of a current source. In the case where the third transistor is off and the fourth transistor is on, the latch circuit is supplied with a first input signal supplied to the first input/output terminal and a second input signal supplied to the second input/output terminal. In the case where the third transistor is on and the fourth transistor is off, an inverted signal of the first input signal is output to the first input/output terminal of the latch circuit, and an inverted signal of the second input signal is output to the second input/output terminal of the latch circuit. The first circuit and the second circuit increase the output gain of the latch circuit.

    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 审中-公开
    电路，其驱动方法和半导体器件

    公开(公告)号：US20160379564A1

    公开(公告)日：2016-12-29

    申请号：US15183892

    申请日：2016-06-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Yoshiyuki KUROKAWA ,  Takashi NAKAGAWA ,  Fumika AKASAWA

    IPC: G09G3/3241

    CPC classification number: G05F3/262 ,  G05F3/26 ,  G09G3/2011 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2330/021 ,  G11C27/024 ,  H01L27/1225

    Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.

    Abstract translation: 电路包括包括第一和第二晶体管的电流镜电路（CM电路），漏极电连接到第二晶体管的漏极的第三晶体管，控制来自电路的电流输出的开关以及第一和第二存储器电路。 CM电路的参考电流被输入到第一晶体管的漏极; 作为参考电流的副本的电流从第二晶体管的漏极输出。 当从电路输出电流时，参考电流不输入到CM电路。 与存储在第一存储器电路中的电压相对应的漏极电流流过第二晶体管; 与存储在第二存储器电路中的电压相对应的漏极电流流过第三晶体管。 两个漏极电流之间的差值对应于电路的输出电流。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160142047A1

    公开(公告)日：2016-05-19

    申请号：US15001338

    申请日：2016-01-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Kei TAKAHASHI ,  Tatsuya ONUKI

    IPC: H03K5/24

    CPC classification number: H03K5/2481 ,  G11C27/024 ,  G11C27/026 ,  H03K5/249

    Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.

    Abstract translation: 包括晶体管和电容器的采样保持电路连接到差分电路。 采样保持电路通过采样操作对电容器进行充电或放电来获取用于校正差分电路的偏移电压的电压。 然后，它通过保持操作保持电容器的电位。 在差分电路的正常工作中，差分电路的输出电位由电容器保持的电位进行校正。 采样保持电路中的晶体管优选地是使用氧化物半导体形成沟道的晶体管。 氧化物半导体晶体管具有极低的漏电流; 因此，可以使采样保持电路的电容器中保持的电位变化最小化。

    DC CONVERTER CIRCUIT AND POWER SUPPLY CIRCUIT
    8.
    发明申请
    DC CONVERTER CIRCUIT AND POWER SUPPLY CIRCUIT 有权
    直流转换电路和电源电路

    公开(公告)号：US20150108959A1

    公开(公告)日：2015-04-23

    申请号：US14580279

    申请日：2014-12-23

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kei TAKAHASHI ,  Yoshiaki ITO ,  Hiroki INOUE ,  Tatsuji NISHIJIMA

    IPC: H02M3/156

    CPC classification number: H02M3/156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869 ,  H02M3/155

    Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.

    Abstract translation: 提供了具有高可靠性的DC转换器电路。 DC转换器电路包括：电感器，被配置为根据流动电流的变化产生电动势; 包括栅极，源极和漏极的晶体管，其被配置为通过导通或关断来控制电感器中的电动势的产生; 当晶体管截止时处于导通状态的整流器; 以及被配置为控制晶体管的导通和截止的控制电路。 晶体管包括作为沟道形成层的氢浓度小于或等于5×1019原子/ cm3的氧化物半导体层。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20130181216A1

    公开(公告)日：2013-07-18

    申请号：US13795244

    申请日：2013-03-12

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Toshihiko SAITO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Hiroki INOUE

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

    Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

    Abstract translation: 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

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