公开(公告)号：US20220115264A1

公开(公告)日：2022-04-14

申请号：US17645888

申请日：2021-12-23

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shengfen CHIU ,  Liang CHEN ,  Liang HAN

IPC分类号： H01L21/764 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11521 ,  H01L29/49 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06

摘要： A method for manufacturing a flash memory device is provided. The method includes: providing a substrate structure including a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, and a gap structure between the gate structures; forming an overhang surrounding an upper portion of the gate structures to form a gap structure between the gate structures; and forming a second isolation region filling an upper portion of the gap structures and leaving a first air gap between the gap structures.

公开(公告)号：US20180197778A1

公开(公告)日：2018-07-12

申请号：US15862100

申请日：2018-01-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang HAN ,  Sheng Fen CHIU ,  Liang CHEN

IPC分类号： H01L21/82 ,  H01L27/11519

CPC分类号： H01L21/82 ,  H01L21/28273 ,  H01L27/11519 ,  H01L29/42324

摘要： A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

公开(公告)号：US20230255024A1

公开(公告)日：2023-08-10

申请号：US18135552

申请日：2023-04-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang HAN ,  Hai Ying WANG

IPC分类号： H10B41/30 ,  H01L29/49 ,  H10B41/60

CPC分类号： H10B41/30 ,  H01L29/4933 ,  H10B41/60

摘要： A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

公开(公告)号：US20210118893A1

公开(公告)日：2021-04-22

申请号：US17028673

申请日：2020-09-22

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang HAN ,  Hai Ying WANG

IPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.