公开(公告)号：US20180197778A1

公开(公告)日：2018-07-12

申请号：US15862100

申请日：2018-01-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Liang HAN ,  Sheng Fen CHIU ,  Liang CHEN

IPC分类号： H01L21/82 ,  H01L27/11519

CPC分类号： H01L21/82 ,  H01L21/28273 ,  H01L27/11519 ,  H01L29/42324

摘要： A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.

公开(公告)号：US20190237478A1

公开(公告)日：2019-08-01

申请号：US16379422

申请日：2019-04-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shan Rong LI ,  Min-hwa CHI ,  Sheng Fen CHIU

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/788 ,  H01L29/04 ,  H01L29/47 ,  H01L29/16 ,  H01L29/78

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/7839 ,  H01L29/7889 ,  H01L29/7926

摘要： A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

公开(公告)号：US20180122823A1

公开(公告)日：2018-05-03

申请号：US15797884

申请日：2017-10-30

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shan Rong LI ,  Min-hwa CHI ,  Sheng Fen CHIU

IPC分类号： H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47

CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47 ,  H01L29/7839 ,  H01L29/7889 ,  H01L29/7926

摘要： A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

公开(公告)号：US20180277600A1

公开(公告)日：2018-09-27

申请号：US15927665

申请日：2018-03-21

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Sheng Fen CHIU ,  Heng CAO

IPC分类号： H01L27/24 ,  H01L29/06 ,  H01L45/00 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L27/2409 ,  H01L21/265 ,  H01L21/76224 ,  H01L27/2463 ,  H01L29/0649 ,  H01L45/1233 ,  H01L45/16

摘要： A memory cell includes a substrate including a first diode region, a second diode region, a third diode region, and a fourth diode region, a first well region formed in the first diode region and the second diode region, a second well region formed in the third diode region and the fourth diode region, a doped conductive region formed on the first well region and the second well region, and a deep trench isolation structure formed in the substrate to electrically isolate different portions of each of the first well region, the second well region, and the doped conductive region formed over different diode regions. The second well region and the first well region have different doping types. The memory cell includes a resistance random access memory device formed over the substrate and electrically connected to the doped conductive region in the second diode region and the third diode region.

公开(公告)号：US20180158832A1

公开(公告)日：2018-06-07

申请号：US15890062

申请日：2018-02-06

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Guan Hua LI ,  Hae Wan YANG ,  Sheng Fen CHIU

IPC分类号： H01L27/11521 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/511 ,  H01L29/66825

摘要： A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality of stacked structures by etching the stacked layer and the substrate, where the spacing between the adjacent stacked structures forms a plurality of parallel first trenches. In addition, the method includes forming a plurality of second trenches and forming a plurality of third trenches. Moreover, the method includes forming a second dielectric layer on the floating gate layer and the side wall and bottom of the third trenches and forming a control gate layer on the second dielectric layer. Further, the method includes forming a plurality of fourth trenches and removing the sacrificial layer along the fourth trenches.

公开(公告)号：US20170287922A1

公开(公告)日：2017-10-05

申请号：US15452869

申请日：2017-03-08

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Guan Hua LI ,  Hae Wan YANG ,  Sheng Fen CHIU

IPC分类号： H01L27/11521 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/511 ,  H01L29/66825

摘要： A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality of stacked structures by etching the stacked layer and the substrate, where the spacing between the adjacent stacked structures forms a plurality of parallel first trenches. In addition, the method includes forming a plurality of second trenches and forming a plurality of third trenches. Moreover, the method includes forming a second dielectric layer on the floating gate layer and the side wall and bottom of the third trenches and forming a control gate layer on the second dielectric layer. Further, the method includes forming a plurality of fourth trenches and removing the sacrificial layer along the fourth trenches.