公开(公告)号：US07110301B2

公开(公告)日：2006-09-19

申请号：US10982247

申请日：2004-11-03

申请人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim ,  Dae-Sik Park ,  Jin-Yub Lee

发明人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim ,  Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/20

摘要： A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

摘要翻译： 非挥发性半导体存储器件包括存储器块和擦除控制器，其被配置为控制多块擦除操作，其中至少两个存储块被同时擦除。 根据一些实施例，在选择并同时擦除所选择的存储块之后，根据外部提供的擦除验证命令和块地址执行针对每个被擦除的存储器块的擦除验证操作。 根据一些实施例，如果在擦除所选择的存储器块期间由存储器件接收到暂停命令，则擦除操作停止，并且开始诸如读取操作的另一操作。 当存储器件接收到恢复命令时，擦除操作恢复。 描述和要求保护其他实施例。

公开(公告)号：US20050248993A1

公开(公告)日：2005-11-10

申请号：US10982247

申请日：2004-11-03

申请人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim ,  Dae-Sik Park ,  Jin-Yub Lee

发明人： Seok-Heon Lee ,  Young-Joon Choi ,  Tae-Gyun Kim ,  Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/14 ,  G11C16/06 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/20

摘要： A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

摘要翻译： 非挥发性半导体存储器件包括存储器块和擦除控制器，其被配置为控制多块擦除操作，其中至少两个存储块被同时擦除。 根据一些实施例，在选择并同时擦除所选择的存储块之后，根据外部提供的擦除验证命令和块地址执行针对每个被擦除的存储器块的擦除验证操作。 根据一些实施例，如果在擦除所选择的存储器块期间由存储器件接收到暂停命令，则擦除操作停止，并且开始诸如读取操作的另一操作。 当存储器件接收到恢复命令时，擦除操作恢复。 描述和要求保护其他实施例。

公开(公告)号：US07210012B2

公开(公告)日：2007-04-24

申请号：US10417770

申请日：2003-04-17

申请人： Jin-Yub Lee ,  Seok-Heon Lee ,  Young-Joon Choi

发明人： Jin-Yub Lee ,  Seok-Heon Lee ,  Young-Joon Choi

IPC分类号： G06F12/14

CPC分类号： G06F12/1441

摘要： A non-volatile semiconductor memory device and/or a data processing system include a non-volatile memory array having a plurality of memory blocks and a write-protection control circuit that controls access to blocks of memory based on a start block address and an end block address. The write-protection control circuit may store start and end block addresses of an unlock region of the non-volatile memory array, and selectively activate a write enable signal according to the relationship between a write address and the start and end block addresses.

摘要翻译： 非易失性半导体存储器件和/或数据处理系统包括具有多个存储器块的非易失性存储器阵列和写保护控制电路，其基于起始块地址和结束来控制对存储器块的访问 块地址。 写保护控制电路可以存储非易失性存储器阵列的解锁区域的开始和结束块地址，并且根据写地址和开始和结束块地址之间的关系选择性地激活写使能信号。

公开(公告)号：US20070183221A1

公开(公告)日：2007-08-09

申请号：US11567895

申请日：2006-12-07

申请人： DAE-SIK PARK ,  Jin-Yub Lee

发明人： DAE-SIK PARK ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US07773415B2

公开(公告)日：2010-08-10

申请号：US12292741

申请日：2008-11-25

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.

摘要翻译： 闪速存储器件包括存储块，其包括布置在第一选择线和第二选择线之间的字线，所述字线被分成第一组和第二组，控制逻辑被配置为确定第一和第二组的激活顺序， 第二选择线，并且确定要提供给未选字线的第一和第二读取电压，所述控制逻辑根据所选择的字线是否属于所述第一组或所述第二组来确定所述激活顺序;以及行选择电路， 在读取操作期间，利用第一和第二读取电压驱动未选择的字线，并根据控制逻辑激活第一和第二选择线。

公开(公告)号：US07486570B2

公开(公告)日：2009-02-03

申请号：US11320975

申请日：2005-12-30

申请人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

发明人： Dae-Sik Park ,  Jin-Yub Lee ,  Seong-Kue Jo

IPC分类号： G11C7/10

CPC分类号： G11C16/10

摘要： Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

摘要翻译： 公开了一种闪存器件的程序方法，包括： 将数据存储在缓冲存储器中并产生高电压作为字线电压。 当数据传送到缓冲存储器完成时，程序方法将缓冲存储器中的数据同时传送到页缓冲电路，并根据字线电压对存储单元阵列中的页缓冲电路中的数据进行编程。

公开(公告)号：US20080205142A1

公开(公告)日：2008-08-28

申请号：US12115827

申请日：2008-05-06

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/14

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括一个电压电平检测单元，一个执行时间检查单元和一个放电 单元。 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US07382663B2

公开(公告)日：2008-06-03

申请号：US11567895

申请日：2006-12-07

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US07643351B2

公开(公告)日：2010-01-05

申请号：US12115827

申请日：2008-05-06

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US20090135658A1

公开(公告)日：2009-05-28

申请号：US12292741

申请日：2008-11-25

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.

摘要翻译： 闪速存储器件包括存储块，其包括布置在第一选择线和第二选择线之间的字线，所述字线被分成第一组和第二组，控制逻辑被配置为确定第一和第二组的激活顺序， 第二选择线，并且确定要提供给未选字线的第一和第二读取电压，所述控制逻辑根据所选择的字线是否属于所述第一组或所述第二组来确定所述激活顺序;以及行选择电路， 在读取操作期间，利用第一和第二读取电压驱动未选择的字线，并根据控制逻辑激活第一和第二选择线。