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    Memory devices having controllers that divide command signals into two signals and systems including such memory devices
    1.
    发明授权
    Memory devices having controllers that divide command signals into two signals and systems including such memory devices 有权
    具有将命令信号分成两个信号的控制器的存储器件和包括这种存储器件的系统

    公开(公告)号：US08576644B2

    公开(公告)日：2013-11-05

    申请号：US13348672

    申请日：2012-01-12

    申请人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    发明人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F11/1048 ,  G06F2213/0038 ,  G11C7/109 ,  G11C7/22 ,  G11C2029/0411

    摘要： A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

    摘要翻译： 提供了使用纠错码的存储装置和包括该存储装置的系统。 存储器件包括一个包括多个位线和多个存储单元的存储单元阵列; 访问所述存储单元阵列的访问块; 以及控制器块，用于接收第一操作命令信号，基于预定准则将第一操作命令信号划分为与至少两个路径相对应的至少两个路径脉冲信号，然后提供至少两个路径脉冲信号 到访问块。 访问块基于控制器块的输出信号进行操作。

    Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices
    2.
    发明申请
    Memory Devices Having Controllers that Divide Command Signals Into Two Signals and Systems Including Such Memory Devices 有权
    具有把命令信号分成包含这种存储器件的两个信号和系统的控制器的存储器件

    公开(公告)号：US20120182815A1

    公开(公告)日：2012-07-19

    申请号：US13348672

    申请日：2012-01-12

    申请人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    发明人： Seong Hyun Jeon ,  Hoi Ju Chung ,  Jung Sunwoo

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F11/1048 ,  G06F2213/0038 ,  G11C7/109 ,  G11C7/22 ,  G11C2029/0411

    摘要： A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

    摘要翻译： 提供了使用纠错码的存储装置和包括该存储装置的系统。 存储器件包括一个包括多个位线和多个存储单元的存储单元阵列; 访问所述存储单元阵列的访问块; 以及控制器块，用于接收第一操作命令信号，基于预定准则将第一操作命令信号划分为与至少两个路径相对应的至少两个路径脉冲信号，然后提供至少两个路径脉冲信号 到访问块。 访问块基于控制器块的输出信号进行操作。

    Refresh circuit and refresh method in semiconductor memory device
    3.
    发明申请
    Refresh circuit and refresh method in semiconductor memory device 有权
    半导体存储器件中的刷新电路和刷新方法

    公开(公告)号：US20080080285A1

    公开(公告)日：2008-04-03

    申请号：US11730275

    申请日：2007-03-30

    申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40618

    摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

    摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
    4.
    发明授权
    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same 有权
    在使用其的半导体存储器件和半导体存储器件中提供电源电压的方法

    公开(公告)号：US07936615B2

    公开(公告)日：2011-05-03

    申请号：US12071348

    申请日：2008-02-20

    申请人： Jung Sunwoo ,  Yun-Sang Lee

    发明人： Jung Sunwoo ,  Yun-Sang Lee

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4096

    摘要： In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

    摘要翻译： 在用于在半导体存储器件中提供电源电压的方法中，第一源电压被施加到存储单元阵列的存储单元，作为用于操作耦合到存储单元的读出放大器的单元阵列内部电压。 施加第二源电压作为存储单元阵列的字线驱动电压。 第二源电压具有高于第一源电压的电压电平的电压电平。 第二源电压也作为输入/输出线驱动器的驱动电压施加，以在写操作模式下将写数据驱动到输入/输出线。

    Refresh circuit and refresh method in semiconductor memory device
    5.
    发明授权
    Refresh circuit and refresh method in semiconductor memory device 有权
    半导体存储器件中的刷新电路和刷新方法

    公开(公告)号：US07844773B2

    公开(公告)日：2010-11-30

    申请号：US11730275

    申请日：2007-03-30

    申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

    IPC分类号： G06F12/00

    CPC分类号： G11C11/406 ,  G11C11/40618

    摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

    摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

    Voltage controlled oscillator and PLL having the same
    6.
    发明授权
    Voltage controlled oscillator and PLL having the same 有权
    压控振荡器和PLL具有相同的功能

    公开(公告)号：US07659785B2

    公开(公告)日：2010-02-09

    申请号：US11769114

    申请日：2007-06-27

    申请人： Jung Sunwoo ,  Young-Don Choi

    发明人： Jung Sunwoo ,  Young-Don Choi

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315 ,  H03L7/0995 ,  H03L2207/06

    摘要： A Voltage Controlled Oscillator (VCO) includes a plurality of oscillation units connected in cascade to form a chain; and a plurality of current source sections operatively connected to the oscillation units, the current source sections each being configured to control current provided to the oscillation units, wherein each of the current source sections includes: at least one fixed current source configured to perform a current control of a corresponding oscillation unit by using a fixed voltage; and at least one variable current source configured to perform a current control of the corresponding oscillation unit by using a variable voltage.

    摘要翻译： 压控振荡器（VCO）包括串联连接以形成链的多个振荡单元; 以及可操作地连接到所述振荡单元的多个电流源部分，所述电流源部分被配置为控制提供给所述振荡单元的电流，其中每个电流源部分包括：至少一个固定电流源，被配置为执行电流 通过使用固定电压控制相应的振荡单元; 以及至少一个可变电流源，被配置为通过使用可变电压来执行对应的振荡单元的电流控制。

    Parameter measurement of semiconductor device from pin with on die termination circuit
    7.
    发明授权
    Parameter measurement of semiconductor device from pin with on die termination circuit 有权
    半导体器件从引脚与芯片端接电路的参数测量

    公开(公告)号：US07245140B2

    公开(公告)日：2007-07-17

    申请号：US10987706

    申请日：2004-11-12

    申请人： Jung Sunwoo ,  Jung-Bae Lee

    发明人： Jung Sunwoo ,  Jung-Bae Lee

    IPC分类号： G01R31/26 ,  G11C7/00

    CPC分类号： G01R31/31713 ,  G01R31/31723

    摘要： A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

    摘要翻译： 半导体器件包括耦合到测试器的ODT（管芯端子）引脚上的测试器端接控制信号。 半导体器件还包括测量路径，该测量路径在测量半导体器件的参数期间将测试器终止控制信号从ODT引脚传输到ODT电路。 ODT引脚和测量路径有利地允许由测试仪控制ODT电路以获得更准确的参数表征。

    Parameter measurement of semiconductor device from pin with on die termination circuit
    8.
    发明申请
    Parameter measurement of semiconductor device from pin with on die termination circuit 有权
    半导体器件从引脚与芯片端接电路的参数测量

    公开(公告)号：US20050253615A1

    公开(公告)日：2005-11-17

    申请号：US10987706

    申请日：2004-11-12

    申请人： Jung Sunwoo ,  Jung-Bae Lee

    发明人： Jung Sunwoo ,  Jung-Bae Lee

    IPC分类号： G11C29/00 ,  G01R31/02 ,  G01R31/317

    CPC分类号： G01R31/31713 ,  G01R31/31723

    摘要： A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

    摘要翻译： 半导体器件包括耦合到测试器的ODT（管芯端子）引脚上的测试器端接控制信号。 半导体器件还包括测量路径，该测量路径在测量半导体器件的参数期间将测试器终止控制信号从ODT引脚传输到ODT电路。 ODT引脚和测量路径有利地允许由测试仪控制ODT电路以获得更准确的参数表征。

    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
    9.
    发明申请
    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same 有权
    在使用其的半导体存储器件和半导体存储器件中提供电源电压的方法

    公开(公告)号：US20090067217A1

    公开(公告)日：2009-03-12

    申请号：US12071348

    申请日：2008-02-20

    申请人： Jung Sunwoo ,  Yun-Sang Lee

    发明人： Jung Sunwoo ,  Yun-Sang Lee

    IPC分类号： G11C11/24 ,  G11C5/14 ,  G11C8/08

    CPC分类号： G11C5/147 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4096

    摘要： In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

    摘要翻译： 在用于在半导体存储器件中提供电源电压的方法中，第一源电压被施加到存储单元阵列的存储单元，作为用于操作耦合到存储单元的读出放大器的单元阵列内部电压。 施加第二源电压作为存储单元阵列的字线驱动电压。 第二源电压具有高于第一源电压的电压电平的电压电平。 第二源电压也作为输入/输出线驱动器的驱动电压施加，以在写操作模式下将写数据驱动到输入/输出线。