公开(公告)号：US07507627B2

公开(公告)日：2009-03-24

申请号：US11686205

申请日：2007-03-14

申请人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jin-Ho Park ,  Seung-Gil Yang ,  Brad H. Lee

发明人： Seong-Hwee Cheong ,  Sang-Woo Lee ,  Jin-Ho Park ,  Seung-Gil Yang ,  Brad H. Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/4234

摘要： In one embodiment, a nonvolatile memory device can be fabricated by forming first metallic dots on a charge storage film using first source gas, forming substitution dots on the charge storage film on which the first metallic dots are formed and forming second metallic dots using a second source gas.

摘要翻译： 在一个实施例中，可以通过使用第一源气体在电荷存储膜上形成第一金属点来形成非易失性存储器件，在形成有第一金属点的电荷存储膜上形成取代点，并使用第二金属点形成第二金属点 源气。

公开(公告)号：US20060246710A1

公开(公告)日：2006-11-02

申请号：US11409685

申请日：2006-04-24

申请人： Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jin-Ho Park

发明人： Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jin-Ho Park

IPC分类号： H01L21/4763 ,  H01L21/76

CPC分类号： H01L27/1108 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L27/0688 ,  H01L27/11

摘要： In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.

摘要翻译： 在形成集成电路器件的方法中，形成延伸穿过第一和第二绝缘层并且穿过其间的半导体层到基板表面的开口。 开口包括在与半导体层相邻的第一和第二绝缘层之间的侧壁中的凹部。 导电插塞形成在开口的侧壁和基板的表面上，并横向延伸到第一和第二绝缘层之间的凹部中以接触半导体层。 可以在侧壁处选择性地蚀刻半导体层，而不必在开口的侧壁基本上蚀刻第一和第二绝缘层，以在第一和第二绝缘层之间形成凹部。 还讨论了相关设备。

公开(公告)号：US07816257B2

公开(公告)日：2010-10-19

申请号：US11409685

申请日：2006-04-24

申请人： Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jin-Ho Park

发明人： Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jin-Ho Park

IPC分类号： H01L21/4763

CPC分类号： H01L27/1108 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L27/0688 ,  H01L27/11

摘要： In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.

摘要翻译： 在形成集成电路器件的方法中，形成延伸穿过第一和第二绝缘层并且穿过其间的半导体层到基板表面的开口。 该开口包括在与半导体层相邻的第一和第二绝缘层之间的侧壁中的凹部。 导电插塞形成在开口的侧壁和基板的表面上，并横向延伸到第一和第二绝缘层之间的凹部中以接触半导体层。 可以在侧壁处选择性地蚀刻半导体层，而不必在开口的侧壁基本上蚀刻第一和第二绝缘层，以在第一和第二绝缘层之间形成凹部。 还讨论了相关设备。

公开(公告)号：US20080136040A1

公开(公告)日：2008-06-12

申请号：US11778344

申请日：2007-07-16

申请人： Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53266 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming electrical interconnects include forming a first electrically insulating layer on a semiconductor substrate and then forming an opening in the first electrically insulating layer. A step is performed to line a sidewall of the opening with a nitrified first metal layer having a non-uniform nitrogen concentration therein. An electrically conductive pattern is formed in the opening. A second metal nitride layer is provided between the electrically conductive pattern and the nitrified first metal layer.

摘要翻译： 形成电互连的方法包括：在半导体衬底上形成第一电绝缘层，然后在第一电绝缘层中形成开口。 进行步骤以使开口的侧壁与其中具有不均匀氮浓度的硝化的第一金属层一起排列。 在开口中形成导电图案。 第二金属氮化物层设置在导电图案和硝化的第一金属层之间。

公开(公告)号：US20060280867A1

公开(公告)日：2006-12-14

申请号：US11361087

申请日：2006-02-22

申请人： Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee

发明人： Jin-Ho Park ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Sang-Woo Lee

IPC分类号： C23C16/00

CPC分类号： C23C16/34 ,  C23C16/4408 ,  C23C16/45561

摘要： An apparatus for depositing a thin film on a substrate includes a processing chamber, supply pipes, and discharge pipes. Each supply pipe is configured to supply a process gas to the processing chamber, and each discharge pipe is connected to one of the supply pipes and an inhale part configured to discharge gas remaining inside the one of the supply pipes. Each of the discharge pipes is separate from one another.

摘要翻译： 用于在基板上沉积薄膜的设备包括处理室，供应管和排出管。 每个供给管被构造成将处理气体供给到处理室，并且每个排出管连接到供应管中的一个和被配置为排出剩余在供给管内的气体的吸入部。 每个排放管彼此分开。

公开(公告)号：US08466556B2

公开(公告)日：2013-06-18

申请号：US13240599

申请日：2011-09-22

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC分类号： H01L29/40

CPC分类号： H01L23/485 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76865 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

公开(公告)号：US20090014879A1

公开(公告)日：2009-01-15

申请号：US12217932

申请日：2008-07-10

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76865 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

摘要翻译： 在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。 绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。 绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。 在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。 因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

公开(公告)号：US20120012969A1

公开(公告)日：2012-01-19

申请号：US13240599

申请日：2011-09-22

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC分类号： H01L27/108

CPC分类号： H01L23/485 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76865 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

摘要翻译： 在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。 绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。 绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。 在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。 因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

公开(公告)号：US08030204B2

公开(公告)日：2011-10-04

申请号：US12217932

申请日：2008-07-10

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Ho-Ki Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76865 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

摘要翻译： 在形成半导体器件的布线结构的方法中，在其上定位有多个导电结构的半导体衬底上形成绝缘层。 绝缘层的上表面被平坦化，并且导电结构之间的空间被绝缘层填充。 绝缘层从衬底部分地移除以形成至少一个开口，衬底通过该开口被部分暴露。 在所述至少一个开口的侧壁的底部和下部形成残余金属层，并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。 因此，可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。

公开(公告)号：US20090035941A1

公开(公告)日：2009-02-05

申请号：US12183421

申请日：2008-07-31

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jun-Ho Park ,  Ho-Ki Lee

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jun-Ho Park ,  Ho-Ki Lee

IPC分类号： C23C16/00 ,  H01L21/44

CPC分类号： H01L21/28562 ,  C23C16/06 ,  C23C16/34 ,  C23C16/45519 ,  C23C16/54 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856

摘要： An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit.

摘要翻译： 一种用于制造半导体器件的设备包括：处理室，被配置为在衬底上执行多个不同的处理。 气体供应单元被配置为向处理室供应至少一种处理气体。 至少一个上电极单元位于处理室的上部。 至少一个下电极单元与上电极单元相对，并且构造成在其上支撑基板。 驱动构件连接到下电极单元和上电极单元中的至少一个，并且被配置为移动下电极单元和/或上电极单元以控制上电极单元和下电极单元之间的距离。 电源单元被配置为向所述上电极单元施加第一电力并且向所述下电极单元施加第二电力。