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    Device for spatially and temporally reordering for data between a processor, memory and peripherals
    1.
    发明授权
    Device for spatially and temporally reordering for data between a processor, memory and peripherals 失效
    用于在处理器，存储器和外围设备之间对数据进行空间和时间重新排序的设备

    公开(公告)号：US06782435B2

    公开(公告)日：2004-08-24

    申请号：US09816066

    申请日：2001-03-26

    申请人： Serafin E. Garcia ,  Zohar B. Bogin ,  Steve Clohset ,  Mikal C. Hunsaker

    发明人： Serafin E. Garcia ,  Zohar B. Bogin ,  Steve Clohset ,  Mikal C. Hunsaker

    IPC分类号： G06F700

    CPC分类号： G06F7/768

    摘要： A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

    摘要翻译： 空间和时间对数据进行处理器，存储器和外围设备的设备。 该设备能够对来自存储器，外围设备和处理器的写入和读取操作的数据进行空间和时间重新排序。 该设备使用外围写入路径空间重新排序单元和外围写入时间重排序单元来重新排列发送到外围设备和存储器的数据。 此外，该设备使用外围读取数据路径空间重新排序单元来重新排序从外围设备读取的数据。 此外，主存储器空间重排序单元用于重新排序从主存储器读取的数据。

    Managing bus transaction dependencies
    4.
    发明授权
    Managing bus transaction dependencies 失效

    公开(公告)号：US06694390B1

    公开(公告)日：2004-02-17

    申请号：US09659108

    申请日：2000-09-11

    申请人： Zohar Bogin ,  Serafin E. Garcia

    发明人： Zohar Bogin ,  Serafin E. Garcia

    IPC分类号： G06F300

    CPC分类号： G06F13/24 ,  G06F13/385

    摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

    Inserting bus inversion scheme in bus path without increased access latency
    5.
    发明授权
    Inserting bus inversion scheme in bus path without increased access latency 失效
    在总线路径中插入总线反演方案，而不增加访问延迟

    公开(公告)号：US06584526B1

    公开(公告)日：2003-06-24

    申请号：US09667049

    申请日：2000-09-21

    申请人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

    发明人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

    IPC分类号： G06F1338

    CPC分类号： G06F11/10 ,  G06F13/4213 ,  G11C7/1078 ,  G11C7/1084

    摘要： A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.

    摘要翻译： 一种在采用总线反转方案时减少总线传输时间的累积延迟的技术。 每当超过一半的数据位有效时，总线反相方案会反转所有数据位，这样在数据传输过程中，总线从不会有更多的一半位有效。 这样可以最大限度地减少任何给定时间内积极驱动总线的驱动电路的数量。 由于需要一定的时间来确定是否有超过一半的位是活动的，所以该过程可以增加总线上的总延迟或数据传输时间。 通过将总线反转功能与还有助于总线等待时间（如纠错码（ECC））计算的另一个功能并行布置，只有更多的时间消耗这两个功能才能增加总线延迟。

    Managing bus transaction dependencies
    8.
    发明授权
    Managing bus transaction dependencies 失效
    管理总线事务依赖关系

    公开(公告)号：US07082480B2

    公开(公告)日：2006-07-25

    申请号：US10674944

    申请日：2003-09-29

    申请人： Zohar Bogin ,  Serafin E. Garcia

    发明人： Zohar Bogin ,  Serafin E. Garcia

    IPC分类号： G06F3/00

    CPC分类号： G06F13/24 ,  G06F13/385

    摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

    摘要翻译： 在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。 在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。 在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。 在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

    Method and apparatus for processing interrupts of a bus
    9.
    发明授权
    Method and apparatus for processing interrupts of a bus 失效
    一种用于处理总线中断的方法和装置

    公开(公告)号：US06983339B1

    公开(公告)日：2006-01-03

    申请号：US09675801

    申请日：2000-09-29

    申请人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

    发明人： Jeffrey L. Rabe ,  Satish Acharya ,  Zohar Bogin ,  Serafin E. Garcia ,  David J. Harriman

    IPC分类号： G06F1/00

    CPC分类号： G06F13/24

    摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

    摘要翻译： 一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。 由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。 标记为最低优先级可重定向的中断根据任务优先级信息重定向。 提供对XTPR事务的支持以更新XTPR寄存器。 提供XTPR更新事务和重定向中断的优先顺序。

    Method and apparatus for improving processor to graphics device throughput
    10.
    发明授权
    Method and apparatus for improving processor to graphics device throughput 有权
    用于提高处理器到图形设备吞吐量的方法和装置

    公开(公告)号：US06433785B1

    公开(公告)日：2002-08-13

    申请号：US09288878

    申请日：1999-04-09

    申请人： Serafin E. Garcia ,  Russell W. Dyer

    发明人： Serafin E. Garcia ,  Russell W. Dyer

    IPC分类号： G06F1316

    CPC分类号： G06F3/14 ,  G06F13/4243

    摘要： An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed. If, however, the timeout counter expires before the posted write buffer becomes available, the memory controller issues a retry response to the processor, indicating to the processor that the first postable write transaction request must be reissued at a later time.

    摘要翻译： 公开了一种通过减少可写入写入事务请求的重试频率来将处理器改善为图形设备吞吐量的存储器控​​制器的实施例。 存储器控制器包括一个发布的写入缓冲器和一个超时计数器。 存储器控制器经由主机总线耦合到处理器，并且还经由图形总线耦合到图形设备。 如果当存储器控制器接收到第一个可写入写入事务请求时，发送的写入缓冲区不可用，则存储器控制器停止主机总线并等待发布的写入缓冲区变得可用。 如果在发送的写入缓冲区不可用时接收到第二个事务请求，则启动超时计数器。 如果发布的写入缓冲区在超时计数器到期之前可用，则第一个可写入写入事务请求完成。 然而，如果超时计数器在发布的写入缓冲器可用之前到期，则存储器控制器向处理器发出重试响应，向处理器指示必须在稍后时间重新发出第一个可写入写入事务请求。