公开(公告)号：US08013612B2

公开(公告)日：2011-09-06

申请号：US12249116

申请日：2008-10-10

申请人： Sergio Morini ,  Marco Giandalia ,  David Respigo ,  Stefano Ruzza ,  Massimo Grasso

发明人： Sergio Morini ,  Marco Giandalia ,  David Respigo ,  Stefano Ruzza ,  Massimo Grasso

IPC分类号： G01R31/02

CPC分类号： G01R31/025 ,  G01R31/34 ,  G01R31/42

摘要： An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.

摘要翻译： 根据本申请的实施例的集成接地故障检测电路包括设置在DC总线的正极轨上的分流电阻器，包括连接到分流电阻器的感觉电路的高压口袋，并且可操作以检测指示 短路和发送器部分，其可操作以连续发送指示故障状况的故障状态信号;以及低压口袋，包括可接收来自感觉电路的故障状态信号的接收器和连接到接收器的逻辑单元，并且可操作 基于故障状态信号提供指示存在故障状况的故障输出信号。

公开(公告)号：US20090102488A1

公开(公告)日：2009-04-23

申请号：US12249116

申请日：2008-10-10

申请人： Sergio Morini ,  Marco Giandalia ,  Davide Respigo ,  Stefano Ruzza ,  Massimo Grasso

发明人： Sergio Morini ,  Marco Giandalia ,  Davide Respigo ,  Stefano Ruzza ,  Massimo Grasso

IPC分类号： G01R31/08

CPC分类号： G01R31/025 ,  G01R31/34 ,  G01R31/42

摘要： An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.

摘要翻译： 根据本申请的实施例的集成接地故障检测电路包括设置在DC总线的正极上的分流电阻器，包括连接到分流电阻器的感觉电路的高压口袋，并且可操作以检测指示 短路和发送器部分，其可操作以连续发送指示故障状况的故障状态信号;以及低压口袋，包括可接收来自感觉电路的故障状态信号的接收器和连接到接收器的逻辑单元，并且可操作 基于故障状态信号提供指示存在故障状况的故障输出信号。

公开(公告)号：US07042325B2

公开(公告)日：2006-05-09

申请号：US10452679

申请日：2003-05-30

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

公开(公告)号：US20060109072A1

公开(公告)日：2006-05-25

申请号：US11324556

申请日：2006-01-03

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US07414507B2

公开(公告)日：2008-08-19

申请号：US11324556

申请日：2006-01-03

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US07864018B2

公开(公告)日：2011-01-04

申请号：US12165749

申请日：2008-07-01

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US20080266043A1

公开(公告)日：2008-10-30

申请号：US12165749

申请日：2008-07-01

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US20060033556A1

公开(公告)日：2006-02-16

申请号：US11199841

申请日：2005-08-09

申请人： Massimo Grasso ,  Sergio Morini

发明人： Massimo Grasso ,  Sergio Morini

IPC分类号： G05F1/10

CPC分类号： H02M3/335 ,  H02M1/36 ,  Y10S323/901

摘要： A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and for dropping the high voltage DC bus voltage to a reduced voltage level at a second terminal; further comprising a low voltage regulator in the package coupled to the second terminal for providing a startup regulated low voltage DC output at a preset level for powering at least one part of the application circuit during startup of the application circuit. The application circuit may be, for example, a switching mode power supply.

摘要翻译： 一种用于将高压DC总线电压的启动电压提供给应用电路的启动电路，所述应用电路包括至少用于驱动所述应用电路的至少一个电源开关的控制电路的集成电路封装; 所述集成电路封装中的降压电阻器具有用于耦合到所述高压DC总线的第一端子和用于在所述第二端子处将所述高压DC总线电压降低到降低的电压电平; 还包括在所述封装中的与所述第二端子耦合的低压调节器，用于提供预设电平的起动调节低压DC输出，以在所述应用电路启动期间为所述施加电路的至少一部分供电。 应用电路可以是例如开关模式电源。

公开(公告)号：US07430131B2

公开(公告)日：2008-09-30

申请号：US11199841

申请日：2005-08-09

申请人： Massimo Grasso ,  Sergio Morini

发明人： Massimo Grasso ,  Sergio Morini

IPC分类号： H02M1/00

CPC分类号： H02M3/335 ,  H02M1/36 ,  Y10S323/901

摘要： A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit including an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and for dropping the high voltage DC bus voltage to a reduced voltage level at a second terminal; and a low voltage regulator in the package coupled to the second terminal for providing a startup regulated low voltage DC output at a preset level for powering at least one part of the application circuit during startup of the application circuit. The application circuit may be, for example, a switching mode power supply.

摘要翻译： 一种用于将高压DC总线电压的启动电压提供给应用电路的启动电路，所述应用电路包括用于至少一个用于驱动所述应用电路的至少一个电源开关的控制电路的集成电路封装; 所述集成电路封装中的降压电阻器具有用于耦合到所述高压DC总线的第一端子和用于在所述第二端子处将所述高压DC总线电压降低到降低的电压电平; 以及耦合到所述第二端子的所述封装中的低电压调节器，用于在启动所述应用电路的过程中提供预设电平的启动调节的低电压DC输出，以对所述应用电路的至少一部分供电。 应用电路可以是例如开关模式电源。

公开(公告)号：US07619450B2

公开(公告)日：2009-11-17

申请号：US12190811

申请日：2008-08-13

申请人： Massimo Grasso ,  Sergio Morini

发明人： Massimo Grasso ,  Sergio Morini

IPC分类号： H03L7/00

CPC分类号： H02M3/335 ,  H02M1/36 ,  Y10S323/901

摘要： A startup circuit for providing a startup voltage from a high voltage DC bus voltage to an application circuit, the startup circuit comprising an integrated circuit package for at least a control circuit for driving at least one power switch of the application circuit having a low voltage terminal; a dropping resistor in the integrated circuit package having a first terminal for coupling to the high voltage DC bus and a second terminal, the dropping resistor dropping the high voltage DC bus voltage to a reduced voltage and providing the reduced voltage at the second terminal; further comprising a low voltage regulator coupled to the second terminal for using the reduced voltage for enabling generation of a regulated startup low voltage DC output at a preset level at the low voltage terminal for powering at least one part of the application circuit during startup of the application circuit, wherein the high voltage DC bus voltage is the only voltage source provided externally to the integrated circuit package.

摘要翻译： 一种用于将高压DC总线电压的启动电压提供给应用电路的启动电路，所述启动电路包括至少一个用于驱动具有低电压端子的应用电路的至少一个电源开关的控制电路的集成电路封装 ; 所述集成电路封装中具有用于耦合到高压DC总线的第一端子和第二端子的降压电阻器，所述降压电阻器将所述高压DC总线电压降低到降低的电压并在所述第二端子处提供降低的电压; 还包括耦合到所述第二端子的低电压调节器，用于使用所述降低的电压，以在所述低电压端子处能够在预定电平下产生调节的启动低压DC输出，以在所述低电压端子的启动期间向所述应用电路的至少一部分供电 应用电路，其中高压DC总线电压是在集成电路封装外部提供的唯一电压源。