公开(公告)号：US20090102488A1

公开(公告)日：2009-04-23

申请号：US12249116

申请日：2008-10-10

申请人： Sergio Morini ,  Marco Giandalia ,  Davide Respigo ,  Stefano Ruzza ,  Massimo Grasso

发明人： Sergio Morini ,  Marco Giandalia ,  Davide Respigo ,  Stefano Ruzza ,  Massimo Grasso

IPC分类号： G01R31/08

CPC分类号： G01R31/025 ,  G01R31/34 ,  G01R31/42

摘要： An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.

摘要翻译： 根据本申请的实施例的集成接地故障检测电路包括设置在DC总线的正极上的分流电阻器，包括连接到分流电阻器的感觉电路的高压口袋，并且可操作以检测指示 短路和发送器部分，其可操作以连续发送指示故障状况的故障状态信号;以及低压口袋，包括可接收来自感觉电路的故障状态信号的接收器和连接到接收器的逻辑单元，并且可操作 基于故障状态信号提供指示存在故障状况的故障输出信号。

公开(公告)号：US08013612B2

公开(公告)日：2011-09-06

申请号：US12249116

申请日：2008-10-10

申请人： Sergio Morini ,  Marco Giandalia ,  David Respigo ,  Stefano Ruzza ,  Massimo Grasso

发明人： Sergio Morini ,  Marco Giandalia ,  David Respigo ,  Stefano Ruzza ,  Massimo Grasso

IPC分类号： G01R31/02

CPC分类号： G01R31/025 ,  G01R31/34 ,  G01R31/42

摘要： An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.

摘要翻译： 根据本申请的实施例的集成接地故障检测电路包括设置在DC总线的正极轨上的分流电阻器，包括连接到分流电阻器的感觉电路的高压口袋，并且可操作以检测指示 短路和发送器部分，其可操作以连续发送指示故障状况的故障状态信号;以及低压口袋，包括可接收来自感觉电路的故障状态信号的接收器和连接到接收器的逻辑单元，并且可操作 基于故障状态信号提供指示存在故障状况的故障输出信号。

公开(公告)号：US07042325B2

公开(公告)日：2006-05-09

申请号：US10452679

申请日：2003-05-30

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

公开(公告)号：US20060109072A1

公开(公告)日：2006-05-25

申请号：US11324556

申请日：2006-01-03

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US07864018B2

公开(公告)日：2011-01-04

申请号：US12165749

申请日：2008-07-01

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US20080266043A1

公开(公告)日：2008-10-30

申请号：US12165749

申请日：2008-07-01

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US07671638B2

公开(公告)日：2010-03-02

申请号：US12146736

申请日：2008-06-26

申请人： Marco Giandalia ,  Sergio Morini ,  Christian Locatelli

发明人： Marco Giandalia ,  Sergio Morini ,  Christian Locatelli

IPC分类号： H03B1/00

CPC分类号： H01L29/7835 ,  H01L27/0255 ,  H01L29/1087 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/00361 ,  H03K19/017545 ,  H03K2217/0081

摘要： A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device. The high-side driver including first and second complementary switched MOSFET series connected at a high-side node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such that if a transient voltage that is negative with respect to the substrate is present at the high-side driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate; a first circuit for controlling the conduction of the first and second MOSFETs to switch the high-side switching device ON and OFF; a diffusion in the N+ epitaxial region in which a terminal connected to the switched node is provided by the diffusion forming the collector of the parasitic transistor; and a second circuit coupled to the diffusion for sensing the high-side driver supply voltage at the epitaxial region and providing a signal to the first circuit to prevent turn-ON of the high-side power switching device.

摘要翻译： 用于驱动具有连接在开关节点处的高低侧功率开关器件的半桥级的驱动电路中的高侧驱动器，驱动高侧电源开关器件的高侧驱动器。 高侧驱动器包括连接在高侧节点处的第一和第二互补开关MOSFET串联，驱动高边功率开关器件，其中一个MOSFET具有形成在衬底之间的寄生双极晶体管，N +外延区连接到 高侧驱动器电源电压和开关节点，寄生晶体管具有由N +外延区域形成的基极，由衬底形成的发射极和由开关节点形成的集电极，使得如果瞬态电压 在高侧驱动器电源电压下存在相对于衬底的负极，寄生晶体管将在开关节点和衬底之间传导短路电流; 第一电路，用于控制第一和第二MOSFET的导通以切换高侧开关装置的ON和OFF; 通过扩散形成寄生晶体管的集电极，在N +外延区域中扩散连接到开关节点的端子; 以及耦合到所述扩散的第二电路，用于感测所述外延区域处的高侧驱动器电源电压，并向所述第一电路提供信号以防止所述高侧电力开关装置的接通。

公开(公告)号：US20090002060A1

公开(公告)日：2009-01-01

申请号：US12146736

申请日：2008-06-26

申请人： Marco Giandalia ,  Sergio Morini ,  Christian Locatelli

发明人： Marco Giandalia ,  Sergio Morini ,  Christian Locatelli

IPC分类号： H03K3/01

CPC分类号： H01L29/7835 ,  H01L27/0255 ,  H01L29/1087 ,  H03K17/162 ,  H03K17/6872 ,  H03K19/00361 ,  H03K19/017545 ,  H03K2217/0081

摘要： A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device. The high-side driver including first and second complementary switched MOSFET series connected at a high-side node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such that if a transient voltage that is negative with respect to the substrate is present at the high-side driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate; a first circuit for controlling the conduction of the first and second MOSFETs to switch the high-side switching device ON and OFF; a diffusion in the N+ epitaxial region in which a terminal connected to the switched node is provided by the diffusion forming the collector of the parasitic transistor; and a second circuit coupled to the diffusion for sensing the high-side driver supply voltage at the epitaxial region and providing a signal to the controller circuit to prevent turn-ON of the high-side power switching device.

摘要翻译： 用于驱动具有连接在开关节点处的高低侧功率开关器件的半桥级的驱动电路中的高侧驱动器，驱动高侧电源开关器件的高侧驱动器。 高侧驱动器包括连接在高侧节点处的第一和第二互补开关MOSFET串联，驱动高边功率开关器件，其中一个MOSFET具有形成在衬底之间的寄生双极晶体管，N +外延区连接到 高侧驱动器电源电压和开关节点，寄生晶体管具有由N +外延区域形成的基极，由衬底形成的发射极和由开关节点形成的集电极，使得如果瞬态电压 在高侧驱动器电源电压下存在相对于衬底的负极，寄生晶体管将在开关节点和衬底之间传导短路电流; 第一电路，用于控制第一和第二MOSFET的导通以切换高侧开关装置的ON和OFF; 通过扩散形成寄生晶体管的集电极，在N +外延区域中扩散连接到开关节点的端子; 以及耦合到扩散的第二电路，用于感测外延区域的高侧驱动器电源电压，并向控制器电路提供信号，以防止高侧功率开关装置的接通。

公开(公告)号：US07414507B2

公开(公告)日：2008-08-19

申请号：US11324556

申请日：2006-01-03

申请人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

发明人： Marco Giandalia ,  Massimo Grasso ,  Marco Passoni

IPC分类号： H01F5/00

CPC分类号： H01F27/323 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/345 ,  H01F2017/0093 ,  H01F2019/085 ,  H01F2027/2819

摘要： A planar transformer arrangement and method provide isolation between an input signal and an output signal. The planar transformer arrangement includes a planar medium having a first layer, a second layer, and a dielectric interlayer arranged between the first and second layers; at least one meandering primary winding arranged on the first layer of the planar medium, a current flow being induced within the primary winding in accordance with the input signal; at least one meandering secondary winding arranged on the second layer of the planar medium, the primary and secondary windings forming a planar transformer, whereby a voltage is induced across the secondary winding in accordance with the current flow within the primary winding; and a mode elimination arrangement configured to produce a compensated voltage by compensating for a common mode interference on the voltage induced across the secondary winding, the mode elimination arrangement being further configured to generate the output signal in accordance with the compensated voltage; wherein the dielectric interlayer of the planar medium provides a voltage isolation between the primary and secondary windings.

摘要翻译： 平面变压器布置和方法提供输入信号和输出信号之间的隔离。 平面变压器布置包括平面介质，其具有布置在第一层和第二层之间的第一层，第二层和介电中间层; 布置在所述平面介质的所述第一层上的至少一个曲折的初级绕组，根据所述输入信号在所述初级绕组内感应出电流; 至少一个曲折的次级绕组布置在所述平面介质的第二层上，所述初级和次级绕组形成平面变压器，由此根据所述初级绕组内的电流流动在所述次级绕组上感应出电压; 以及模式消除装置，其被配置为通过补偿对所述次级绕组两端感应的电压的共模干扰来产生补偿电压，所述模式消除装置还被配置为根据所述补偿电压产生所述输出信号; 其中平面介质的电介质中间层提供初级和次级绕组之间的电压隔离。

公开(公告)号：US06859087B2

公开(公告)日：2005-02-22

申请号：US10696711

申请日：2003-10-29

申请人： Giovanni Galli ,  Marco Giandalia ,  Andrea Merello

发明人： Giovanni Galli ,  Marco Giandalia ,  Andrea Merello

IPC分类号： H01L27/04 ,  H01L21/822 ,  H02M1/00 ,  H02M1/08 ,  H02M1/32 ,  H02M3/337 ,  H03K17/08 ,  H03K17/56 ,  H03K3/00

CPC分类号： H02M1/32 ,  H02M3/3376 ,  H03K17/163 ,  H03K17/168

摘要： A gate drive integrated circuit for switching power transistors using an external controller includes a gate driving capability and low quiescent current and allows use of a bootstrap supply technique for providing the logic supply voltage. The gate driver integrated circuit detects power transistor desaturation, protecting a desaturated transistor from transient over voltages by smoothly turning off the desaturated transistor via a soft shutdown sequence. A fault control circuit of the gate driver integrated circuit manages protection of supply under-voltage and transistor desaturation and is capable of communicating with a plurality of gate driver integrated circuits in a multi-phase system using a dedicated local network.

摘要翻译： 用于使用外部控制器来切换功率晶体管的栅极驱动集成电路包括栅极驱动能力和低静态电流，并且允许使用自举电源技术来提供逻辑电源电压。 栅极驱动器集成电路检测功率晶体管去饱和，通过软关断序列平滑地关闭去饱和晶体管，保护不饱和晶体管免受瞬态过电压的影响。 栅极驱动器集成电路的故障控制电路管理供电欠压和晶体管去饱和的保护，并且能够使用专用的本地网络与多相系统中的多个栅极驱动器集成电路进行通信。