公开(公告)号：US20090267813A1

公开(公告)日：2009-10-29

申请号：US12453109

申请日：2009-04-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M7/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20110128170A1

公开(公告)日：2011-06-02

申请号：US12923858

申请日：2010-10-12

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M7/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US07830280B2

公开(公告)日：2010-11-09

申请号：US12453109

申请日：2009-04-29

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC分类号： H03M5/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于传输的数据，对接收到的数据内的比特数进行加扰，根据给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20080278193A1

公开(公告)日：2008-11-13

申请号：US12219213

申请日：2008-07-17

申请人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

公开(公告)号：US07768298B2

公开(公告)日：2010-08-03

申请号：US12219213

申请日：2008-07-17

申请人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US07403040B2

公开(公告)日：2008-07-22

申请号：US11790014

申请日：2007-04-23

申请人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US07814359B2

公开(公告)日：2010-10-12

申请号：US11612800

申请日：2006-12-19

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发射第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

公开(公告)号：US20090225622A1

公开(公告)日：2009-09-10

申请号：US12430163

申请日：2009-04-27

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US20100091601A1

公开(公告)日：2010-04-15

申请号：US12635751

申请日：2009-12-11

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US20080130811A1

公开(公告)日：2008-06-05

申请号：US12029518

申请日：2008-02-12

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC分类号： H04L7/00 ,  G11B20/20

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

摘要翻译： 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送端接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与施加到发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。