公开(公告)号：US20090140320A1

公开(公告)日：2009-06-04

申请号：US12275369

申请日：2008-11-21

Applicant: Seung-Jun LEE ,  Woon-Kyung LEE

Inventor： Seung-Jun LEE ,  Woon-Kyung LEE

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Abstract translation: 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US20140199815A1

公开(公告)日：2014-07-17

申请号：US14156781

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

Inventor： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC: H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract translation: 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步阶形状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

公开(公告)号：US20140197481A1

公开(公告)日：2014-07-17

申请号：US14156607

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

Inventor： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC: H01L29/78

CPC classification number: H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

Abstract translation: 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

公开(公告)号：US20140197546A1

公开(公告)日：2014-07-17

申请号：US14156827

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

Inventor： Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract translation: 垂直型半导体器件中的阶形形状焊盘结构和布线结构包括具有第一线形状并且在边缘部分的上表面处包括第一焊盘区域的第一导线和具有第二线形并且间隔开的第二导线 并且设置在第一导线上。 第一导线的端部延伸到第一位置。 第二焊盘区域包括在第二导线的边缘部分的上表面上。 第二导线的端部延伸到第一位置。 第二导电线包括在垂直方向上与第一焊盘区域相对的部分处的凹部，以露出第一焊盘区域。 衬垫结构可以用在垂直型非易失性存储器件中。

公开(公告)号：US20120074484A1

公开(公告)日：2012-03-29

申请号：US13223698

申请日：2011-09-01

Applicant: Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

Inventor： Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L21/764 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11526

Abstract: A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成彼此间隔开的多个栅极结构; 形成覆盖所述栅极结构的第一绝缘层，所述第一绝缘层包括所述栅极结构之间的空隙; 去除所述第一绝缘层的上部以在所述栅极结构的下部的侧壁和所述栅极结构之间的所述衬底上形成第一绝缘层图案，所述第一绝缘层图案包括其上的第一凹部; 在由第一绝缘层图案暴露的栅极结构的上部形成导电层; 使导电层与栅极结构反应; 以及在所述栅极结构的上部形成第二绝缘层，所述第二绝缘层包括与所述第一凹部流体连通的第二凹部。

公开(公告)号：US20110059585A1

公开(公告)日：2011-03-10

申请号：US12943366

申请日：2010-11-10

Applicant: Woon-Kyung LEE ,  Jeong-Hyuk CHOI

Inventor： Woon-Kyung LEE ,  Jeong-Hyuk CHOI

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/981

Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.

Abstract translation: 提供了一种非易失性存储器件和制造方法。 非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。 栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。 放电区域。