公开(公告)号：US12128434B2

公开(公告)日：2024-10-29

申请号：US17641572

申请日：2019-12-18

Applicant: Sung Ho Lee ,  Young Ho Lee

Inventor： Sung Ho Lee ,  Young Ho Lee

IPC: B05B17/06 ,  C02F1/461 ,  C02F1/467

CPC classification number: B05B17/06 ,  C02F1/4618 ,  C02F1/467

Abstract: An ultrasonic spray apparatus is configured to minimize contact between bubbles, which are generated due to ultrasonic excitation, and ionized water when the bubbles are discharged. The ultrasonic spray apparatus is configured so that a discharge pipe is installed to start from a bottom or a side surface of an accommodation space storing ionized water and protrude above the ionized water filled in the accommodation space. The bubbles are able to be discharged into the accommodation space through the discharge pipe. Changes in properties of the ionized water may be prevented. The properties of the ionized water may be utilized as they are. The discharge of the bubbles is possible even when anyone of the branched portions is blocked, and interference with a flow of the bubbles is prevented in advance even when water drops or the like generated inside the accommodation space block any one of the branched portions.

公开(公告)号：US20220314261A1

公开(公告)日：2022-10-06

申请号：US17641572

申请日：2019-12-18

Applicant: Sung Ho LEE ,  Young Ho LEE

Inventor： Sung Ho LEE ,  Young Ho LEE

IPC: B05B17/06 ,  C02F1/461 ,  C02F1/467

Abstract: An ultrasonic spray apparatus is configured to minimize contact between bubbles, which are generated due to ultrasonic excitation, and ionized water when the bubbles are discharged. The ultrasonic spray apparatus is configured so that a discharge pipe is installed to start from a bottom or a side surface of an accommodation space storing ionized water and protrude above the ionized water filled in the accommodation space. The bubbles are able to be discharged into the accommodation space through the discharge pipe. Changes in properties of the ionized water may be prevented. The properties of the ionized water may be utilized as they are. The discharge of the bubbles is possible even when anyone of the branched portions is blocked, and interference with a flow of the bubbles is prevented in advance even when water drops or the like generated inside the accommodation space block any one of the branched portions.

公开(公告)号：US09117654B2

公开(公告)日：2015-08-25

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L21/467 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/544 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US20140191405A1

公开(公告)日：2014-07-10

申请号：US14208456

申请日：2014-03-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08693612B2

公开(公告)日：2014-04-08

申请号：US12557939

申请日：2009-09-11

Applicant: Young Ho Lee ,  Kang Hee Lee ,  Jae Yong Kim ,  Kyung Ho Yoon ,  Hyung Kyu Kim ,  Chang Hwan Shin ,  Dong Seok Oh ,  Wang Ki In ,  Tae Hyun Chun ,  Kun Woo Song

Inventor： Young Ho Lee ,  Kang Hee Lee ,  Jae Yong Kim ,  Kyung Ho Yoon ,  Hyung Kyu Kim ,  Chang Hwan Shin ,  Dong Seok Oh ,  Wang Ki In ,  Tae Hyun Chun ,  Kun Woo Song

IPC: G21C3/34

CPC classification number: G21C3/352 ,  G21C3/356 ,  Y02E30/40

Abstract: A spacer grid for nuclear fuel rods includes a plurality of unit spacer grids stacked one on top of another. Each unit spacer grid includes a plurality of unit spacer grid straps disposed at regular intervals in a row, and a plurality of fixing grid straps connected to respective opposite ends of the unit spacer grid straps so as to fix the unit spacer grid straps. Each unit spacer grid strap has convexities alternating with each other on opposite sides thereof at regular intervals, and at least one of the convexities has a diameter greater than the others. The unit spacer grids are rotated in one direction by a 90 or 180 degree angle when being stacked.

Abstract translation: 用于核燃料棒的间隔栅格包括多个堆叠在另一个顶部上的单元间隔栅格。 每个单元间隔栅格包括以规则的间隔布置成一排的多个单元隔离栅格带，以及连接到单元间隔栅格带的相应相对端的多个固定网格带，以固定单元间隔网格带。 每个单元间隔网格带在其相对侧上以规则的间隔彼此交替的凸起，并且至少一个凸起的直径大于其他直径。 当堆叠时，单元间隔栅格在一个方向上旋转90或180度。

公开(公告)号：US20140054787A1

公开(公告)日：2014-02-27

申请号：US13973627

申请日：2013-08-22

Applicant: Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

Inventor： Dongseog EUN ,  Young-Ho LEE ,  Joonhee LEE ,  Seok-won LEE ,  Yoocheol SHIN

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/49844 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract translation: 提供了形成由此制造的电极堆叠和三维半导体器件的方法。 该装置可以包括依次层叠在基板上以构成电极结构的电极。 每个电极可以包括从位于其上的一个电极的侧壁水平和向外突出的连接部分和具有与位于其上的电极之一的侧壁共面的对准部分。 这里，彼此垂直相邻设置的电极中的至少两个可以以这样的方式设置，使得其对准的部分具有基本上对准以彼此共面的侧壁。

公开(公告)号：US08541775B2

公开(公告)日：2013-09-24

申请号：US13331698

申请日：2011-12-20

Applicant: Seung Beom Baek ,  Young Ho Lee ,  Jin Ku Lee ,  Mi Ri Lee

Inventor： Seung Beom Baek ,  Young Ho Lee ,  Jin Ku Lee ,  Mi Ri Lee

IPC: H01L21/02

CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract translation: 肖特基二极管，包括肖特基二极管的电阻式存储器件及其制造方法。 电阻式存储器件包括一个包括字线，形成在字线上的肖特基二极管和形成在肖特基二极管上的存储层的半导体衬底。 肖特基二极管包括第一半导体层，形成在第一半导体层上并具有比第一半导体层低的功函数的导电层和形成在导电层上的第二半导体层。

公开(公告)号：US20120305876A1

公开(公告)日：2012-12-06

申请号：US13331698

申请日：2011-12-20

Applicant: Seung Beom BAEK ,  Young Ho LEE ,  Jin Ku LEE ,  Mi Ri LEE

Inventor： Seung Beom BAEK ,  Young Ho LEE ,  Jin Ku LEE ,  Mi Ri LEE

IPC: H01L45/00 ,  H01L29/872 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

Abstract translation: 肖特基二极管，包括肖特基二极管的电阻式存储器件及其制造方法。 电阻式存储器件包括一个包括字线，形成在字线上的肖特基二极管和形成在肖特基二极管上的存储层的半导体衬底。 肖特基二极管包括第一半导体层，形成在第一半导体层上并具有比第一半导体层低的功函数的导电层和形成在导电层上的第二半导体层。

公开(公告)号：US20120302024A1

公开(公告)日：2012-11-29

申请号：US13560577

申请日：2012-07-27

Applicant: Young-Ho LEE ,  Seung-Joon JEON ,  Tae-Hang AHN

Inventor： Young-Ho LEE ,  Seung-Joon JEON ,  Tae-Hang AHN

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract translation: 半导体器件包括：衬底上的栅极图案; 在栅极图案的两侧设置在基板中的凹部图案，每个凹部图案具有在栅极图案下方延伸的侧表面; 以及填充凹陷图案的源极和漏极，并且在栅极图案下形成应变通道。

公开(公告)号：US08318603B2

公开(公告)日：2012-11-27

申请号：US12653588

申请日：2009-12-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。