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    Source transistor configurations and control methods
    4.
    发明授权
    Source transistor configurations and control methods 失效
    源晶体管配置和控制方法

    公开(公告)号：US07705625B2

    公开(公告)日：2010-04-27

    申请号：US11483263

    申请日：2006-07-06

    申请人： Seung-Moon Yoo ,  Jae Hoon Yoo ,  Jeongduk Sohn ,  Sung Ju Son ,  Myung Chan Choi ,  Young Tae Kim ,  Oh Sang Yoon ,  Sang-Kyun Han

    发明人： Seung-Moon Yoo ,  Jae Hoon Yoo ,  Jeongduk Sohn ,  Sung Ju Son ,  Myung Chan Choi ,  Young Tae Kim ,  Oh Sang Yoon ,  Sang-Kyun Han

    IPC分类号： H03K19/094

    CPC分类号： H03K19/0016 ,  G11C7/1045 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

    摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

    摘要翻译： 源晶体管配置被描述为减少集成电路内的泄漏和延迟。 使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。 这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。 描述了用于驱动这些源堆栈的装置。 在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。 还描述了诸如晶体管的定向放置的其它技术。

    Dynamic memory refresh configurations and leakage control methods
    5.
    发明授权
    Dynamic memory refresh configurations and leakage control methods 失效
    动态内存刷新配置和泄漏控制方法

    公开(公告)号：US07522464B2

    公开(公告)日：2009-04-21

    申请号：US11779716

    申请日：2007-07-18

    申请人： Seung-Moon Yoo ,  Myung Chan Choi ,  Sangho Shin ,  Sang-Kyun Han

    发明人： Seung-Moon Yoo ,  Myung Chan Choi ,  Sangho Shin ,  Sang-Kyun Han

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/4094 ,  G11C29/783 ,  G11C29/83 ,  G11C29/832 ,  G11C2211/4061 ,  G11C2211/4065 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.

    摘要翻译： 描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。 根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线 在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。 在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。 刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

    DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS
    6.
    发明申请
    DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS 失效
    动态记忆刷新配置和泄漏控制方法

    公开(公告)号：US20080031068A1

    公开(公告)日：2008-02-07

    申请号：US11779716

    申请日：2007-07-18

    申请人： Seung-Moon Yoo ,  Myung Choi ,  Sangho Shin ,  Sang-Kyun Han

    发明人： Seung-Moon Yoo ,  Myung Choi ,  Sangho Shin ,  Sang-Kyun Han

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/4094 ,  G11C29/783 ,  G11C29/83 ,  G11C29/832 ,  G11C2211/4061 ,  G11C2211/4065 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.

    摘要翻译： 描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。 根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线 在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。 在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。 刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

    Source transistor configurations and control methods
    7.
    发明申请
    Source transistor configurations and control methods 失效
    源晶体管配置和控制方法

    公开(公告)号：US20070063763A1

    公开(公告)日：2007-03-22

    申请号：US11483263

    申请日：2006-07-06

    申请人： Seung-Moon Yoo ,  Jae Yoo ,  Jeongduk Sohn ,  Sung Son ,  Myung Choi ,  Young Kim ,  Oh Yoon ,  Sang-Kyun Han

    发明人： Seung-Moon Yoo ,  Jae Yoo ,  Jeongduk Sohn ,  Sung Son ,  Myung Choi ,  Young Kim ,  Oh Yoon ,  Sang-Kyun Han

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0016 ,  G11C7/1045 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

    摘要： Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

    摘要翻译： 源晶体管配置被描述为减少集成电路内的泄漏和延迟。 使用堆叠晶体管配置（例如在第一虚拟电源连接和VSS之间的两个晶体管堆叠）和第二虚拟电源连接和VDD之间来支持虚拟电源和接地节点。 这些堆叠晶体管的栅极驱动器响应于电路的工作功率模式，例如主动模式，主动待机模式和深度掉电模式，以不同的电压电平进行调制。 描述了用于驱动这些源堆栈的装置。 在一个实施例中，单独的虚拟节点适用于不同类型的电路，例如缓冲器，行地址选通和列地址选通。 还描述了诸如晶体管的定向放置的其它技术。