公开(公告)号：US20070291170A1

公开(公告)日：2007-12-20

申请号：US11760806

申请日：2007-06-11

申请人： Seung-hoon Han ,  Seung-joon Yang ,  Rae-hong Park ,  Jun-yong Kim

发明人： Seung-hoon Han ,  Seung-joon Yang ,  Rae-hong Park ,  Jun-yong Kim

IPC分类号： G06K9/32 ,  H04N7/01

CPC分类号： G06T3/4084 ,  G06T7/13 ,  H04N7/014 ,  H04N7/0142

摘要： An image resolution conversion method and apparatus based on a projection onto convex sets (POCS) method are provided. The image resolution conversion method comprises detecting an edge region and a direction of the edge region in an input low-resolution image frame in order to generate an edge map and edge direction information, generating a directional point spread function based on the edge map and the edge direction information, interpolating the input low-resolution image frame into a high-resolution image frame, generating a residual term based on the input low-resolution image frame, the high-resolution image frame, and the directional point spread function, and renewing the high-resolution image frame according to a result of comparing the residual term with a threshold.

摘要翻译： 提供了一种基于投影到凸集（POCS）方法的图像分辨率转换方法和装置。 图像分辨率转换方法包括检测输入低分辨率图像帧中的边缘区域和边缘区域的方向，以便生成边缘图和边缘方向信息，基于边缘图生成定向点扩展函数， 边缘方向信息，将输入的低分辨率图像帧内插到高分辨率图像帧中，基于输入的低分辨率图像帧，高分辨率图像帧和方向点扩展函数生成残余项，并且更新 根据将剩余项与阈值进行比较的结果的高分辨率图像帧。

公开(公告)号：US07535052B2

公开(公告)日：2009-05-19

申请号：US11763137

申请日：2007-06-14

申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US20090159952A1

公开(公告)日：2009-06-25

申请号：US12397543

申请日：2009-03-04

申请人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L29/68

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US08030150B2

公开(公告)日：2011-10-04

申请号：US12397543

申请日：2009-03-04

申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US20080017915A1

公开(公告)日：2008-01-24

申请号：US11763137

申请日：2007-06-14

申请人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L27/105 ,  H01L21/8229

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。