公开(公告)号：US09728535B2

公开(公告)日：2017-08-08

申请号：US15058664

申请日：2016-03-02

申请人： Young-sang Youn ,  Myung-geun Song ,  Ji-hoon Cha ,  Jae-jik Baek ,  Bo-un Yoon ,  Jeong-nam Han

发明人： Young-sang Youn ,  Myung-geun Song ,  Ji-hoon Cha ,  Jae-jik Baek ,  Bo-un Yoon ,  Jeong-nam Han

IPC分类号： H01L21/76 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/06

CPC分类号： H01L21/76229 ,  H01L21/2652 ,  H01L21/763 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657

摘要： A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

公开(公告)号：US20160315045A1

公开(公告)日：2016-10-27

申请号：US15016376

申请日：2016-02-05

申请人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

发明人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0886

摘要： The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

摘要翻译： 半导体器件可以在衬底上包括绝缘中间层，衬底包括其上部的接触区域，穿过绝缘中间层并接触接触区域的主接触插塞，具有柱形形状的主接触插塞包括 第一屏障图案和第一金属图案，以及围绕主接触插塞的上侧壁的延伸图案，延伸图案包括阻挡材料。 在半导体器件中，接触结构和其上的布线之间的对准边缘可能增加。 此外，可以减小接触结构和栅电极之间的短路故障。

公开(公告)号：US20160284699A1

公开(公告)日：2016-09-29

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/6656

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

摘要翻译： 提供半导体器件。 半导体器件包括限定衬底上的沟槽并包括上部和下部的栅极间隔物，栅极绝缘膜，其沿着沟槽的侧壁和底表面延伸并且不与所述沟槽的上部接触 栅极间隔物，沿着沟槽的侧壁和底面在栅极绝缘膜上延伸的下部导电膜，并且不与栅极间隔物的上部重叠，并且栅极绝缘的最上部的上部导电膜 在下导电膜上的膜。

公开(公告)号：US20160181243A1

公开(公告)日：2016-06-23

申请号：US15058664

申请日：2016-03-02

申请人： Young-sang Youn ,  Myung-geun Song ,  Ji-hoon Cha ,  Jae-jik Baek ,  Bo-un Yoon ,  Jeong-nam Han

发明人： Young-sang Youn ,  Myung-geun Song ,  Ji-hoon Cha ,  Jae-jik Baek ,  Bo-un Yoon ,  Jeong-nam Han

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L21/76229 ,  H01L21/2652 ,  H01L21/763 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657

摘要： A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

摘要翻译： 一种制造半导体器件的方法包括：通过在衬底中形成以第一间距重复的多个第一器件隔离沟槽来形成多个鳍片，形成从第一器件隔离的顶表面突出的多个翅片型有源区域 通过在所述多个第一器件隔离沟槽中形成所述第一器件隔离层，通过蚀刻所述衬底和所述第一器件隔离层的一部分来形成以与所述第一间距不同的间距隔离沟槽的多个第二器件， 在所述多个第二器件隔离沟槽中的第二器件隔离层，以便形成彼此分离的多个鳍式有源区域组，其间具有第二器件隔离层。

公开(公告)号：US09299700B2

公开(公告)日：2016-03-29

申请号：US14639494

申请日：2015-03-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US08916460B1

公开(公告)日：2014-12-23

申请号：US14270315

申请日：2014-05-05

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US08652915B2

公开(公告)日：2014-02-18

申请号：US13212380

申请日：2011-08-18

申请人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Kevin Ahn ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L21/02532 ,  H01L21/0262 ,  H01L21/3083 ,  H01L29/66545 ,  H01L29/66636

摘要： A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.

摘要翻译： 半导体器件的制造方法可以通过蚀刻位于紧邻的栅电极结构之间的衬底中的预备沟槽的侧壁，从而在栅极电极结构之下进一步凹入侧壁以提供凹入的侧壁。 然后，可以使用晶体各向异性蚀刻来蚀刻预备沟槽的凹陷侧壁和底部，以在衬底中形成六边形形状的沟槽。

公开(公告)号：US08557651B2

公开(公告)日：2013-10-15

申请号：US13040472

申请日：2011-03-04

申请人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Hag-Ju Cho ,  Sang-Jin Hyun ,  Hoon-Joo Na ,  Hyung-Seok Hong

发明人： Hyo-San Lee ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Hag-Ju Cho ,  Sang-Jin Hyun ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/28

摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.

摘要翻译： 在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。 蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。 因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

公开(公告)号：US20130023100A1

公开(公告)日：2013-01-24

申请号：US13479679

申请日：2012-05-24

申请人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。

公开(公告)号：US08344385B2

公开(公告)日：2013-01-01

申请号：US12872270

申请日：2010-08-31

申请人： Young-Hoo Kim ,  Hyo-San Lee ,  Sang-Won Bae ,  Bo-Un Yoon ,  Kun-Tack Lee

发明人： Young-Hoo Kim ,  Hyo-San Lee ,  Sang-Won Bae ,  Bo-Un Yoon ,  Kun-Tack Lee

IPC分类号： H01L29/06 ,  H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11556 ,  H01L27/11582

摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.

摘要翻译： 在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。 单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。 隧道氧化物层设置在单晶半导体图案上。 在隧道氧化物层和衬底上提供下电极层图案。 在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。 在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。 在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。 在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。