公开(公告)号：US07535052B2

公开(公告)日：2009-05-19

申请号：US11763137

申请日：2007-06-14

Applicant: Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

Inventor： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC: H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

Abstract translation: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US20080176403A1

公开(公告)日：2008-07-24

申请号：US11983281

申请日：2007-11-08

Applicant: Jun-Yong Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Byoung-Ho Kwon

Inventor： Jun-Yong Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Byoung-Ho Kwon

IPC: H01L21/306 ,  C23F1/00

CPC classification number: H01L21/31053 ,  C09G1/02

Abstract: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.

Abstract translation: 在化学和机械抛光层的方法中，制备其上形成有阶梯部分的层的基底。 该层主要在约30℃至约80℃的温度下进行化学和机械抛光，以除去该层的阶梯部分。 在约5℃至约25℃的温度下，该层被二次化学和机械抛光而没有阶梯部分以形成具有期望厚度的平坦层。 因此，可以在初始阶段快速移除阶梯部分，使得该方法可以具有改进的生产量。

公开(公告)号：US20070184663A1

公开(公告)日：2007-08-09

申请号：US11702124

申请日：2007-02-05

Applicant: Jun-Yong Kim ,  Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Sung-Ho Shin

Inventor： Jun-Yong Kim ,  Ho-Young Kim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Sung-Ho Shin

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L21/31053

Abstract: Example embodiments are directed to a method of planarizing a semiconductor device. A first CMP process may be performed on an insulating layer to remove a stepped structure of the insulating layer. A second CMP process may be performed to planarize the insulating layer with the stepped structure removed until a given pattern is exposed. A process temperature of the first CMP process may be higher than that of the second CMP process. Accordingly, an initial stepped structure may be more readily removed in a planarization process of a surface of the semiconductor device, which may reduce the CMP process time and may increase the degree of planarization.

Abstract translation: 示例性实施例涉及一种平面化半导体器件的方法。 可以在绝缘层上执行第一CMP工艺以去除绝缘层的阶梯状结构。 可以执行第二CMP工艺以使去除直到给定图案暴露的阶梯结构的绝缘层平坦化。 第一CMP工艺的工艺温度可以高于第二CMP工艺的工艺温度。 因此，可以在半导体器件的表面的平坦化处理中更容易地去除初始阶梯结构，这可以减少CMP处理时间并且可以增加平坦化程度。

公开(公告)号：US20130158964A1

公开(公告)日：2013-06-20

申请号：US13325403

申请日：2011-12-14

Applicant: Gabriel J. Hall ,  Mauricio F. Ordonez ,  Darren S. Miller ,  Jun Yong Kim ,  Chong Youn Choe ,  Dae Il Kim ,  Hyong Guk Kim

Inventor： Gabriel J. Hall ,  Mauricio F. Ordonez ,  Darren S. Miller ,  Jun Yong Kim ,  Chong Youn Choe ,  Dae Il Kim ,  Hyong Guk Kim

IPC: G06G7/48

CPC classification number: G06Q10/0633 ,  G06Q10/06

Abstract: A method for providing a new workflow that reuses an existing workflow includes displaying one or more collections of existing workflows available for selection; receiving a selection of one of the one or more existing workflow collections; displaying one or more existing workflows associated with the selected existing workflow collection; receiving a selection of one of the existing workflows in the selected existing workflow collection; receiving a selection of a variable in the selected existing workflow to be used in the new workflow; and storing the new workflow such that, when executed, the new workflow utilizes the selected variable from the existing workflow.

Abstract translation: 用于提供重新使用现有工作流的新工作流的方法包括显示可用于选择的现有工作流的一个或多个集合; 接收所述一个或多个现有工作流集合中的一个的选择; 显示与所选择的现有工作流集合相关联的一个或多个现有工作流; 在所选择的现有工作流集合中接收对现有工作流中的一个的选择; 在所选择的现有工作流中接收要在新工作流中使用的变量的选择; 并且存储新的工作流，使得当被执行时，新工作流利用来自现有工作流的所选变量。

公开(公告)号：US20090159952A1

公开(公告)日：2009-06-25

申请号：US12397543

申请日：2009-03-04

Applicant: Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

Inventor： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC: H01L29/68

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

Abstract translation: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US20070291170A1

公开(公告)日：2007-12-20

申请号：US11760806

申请日：2007-06-11

Applicant: Seung-hoon Han ,  Seung-joon Yang ,  Rae-hong Park ,  Jun-yong Kim

Inventor： Seung-hoon Han ,  Seung-joon Yang ,  Rae-hong Park ,  Jun-yong Kim

IPC: G06K9/32 ,  H04N7/01

CPC classification number: G06T3/4084 ,  G06T7/13 ,  H04N7/014 ,  H04N7/0142

Abstract: An image resolution conversion method and apparatus based on a projection onto convex sets (POCS) method are provided. The image resolution conversion method comprises detecting an edge region and a direction of the edge region in an input low-resolution image frame in order to generate an edge map and edge direction information, generating a directional point spread function based on the edge map and the edge direction information, interpolating the input low-resolution image frame into a high-resolution image frame, generating a residual term based on the input low-resolution image frame, the high-resolution image frame, and the directional point spread function, and renewing the high-resolution image frame according to a result of comparing the residual term with a threshold.

Abstract translation: 提供了一种基于投影到凸集（POCS）方法的图像分辨率转换方法和装置。 图像分辨率转换方法包括检测输入低分辨率图像帧中的边缘区域和边缘区域的方向，以便生成边缘图和边缘方向信息，基于边缘图生成定向点扩展函数， 边缘方向信息，将输入的低分辨率图像帧内插到高分辨率图像帧中，基于输入的低分辨率图像帧，高分辨率图像帧和方向点扩展函数生成残余项，并且更新 根据将剩余项与阈值进行比较的结果的高分辨率图像帧。

公开(公告)号：US08030150B2

公开(公告)日：2011-10-04

申请号：US12397543

申请日：2009-03-04

Applicant: Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

Inventor： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC: H01L21/8238

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

Abstract translation: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US20080017915A1

公开(公告)日：2008-01-24

申请号：US11763137

申请日：2007-06-14

Applicant: Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

Inventor： Byoung-ho KWON ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC: H01L27/105 ,  H01L21/8229

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

Abstract translation: 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US5944580A

公开(公告)日：1999-08-31

申请号：US889476

申请日：1997-07-08

Applicant: Yong-Kwon Kim ,  Jun-Yong Kim

Inventor： Yong-Kwon Kim ,  Jun-Yong Kim

IPC: B24B37/07 ,  B24B49/16 ,  H01L21/304 ,  H01L21/306 ,  B24B29/02

CPC classification number: H01L21/02024 ,  B24B37/04 ,  B24B49/16

Abstract: An improved sensing device and method for leveling a semiconductor wafer in a chemical mechanical polishing apparatus, which easily detects the change of pressure from a semiconductor wafer contacting with the polishing surface. The present invention includes a polishing platen having a polishing pad on the upper leveled surface thereof, and fixed to a rotatable platen driving shaft. A carrier is rotatably provided on the upper surface of the polishing platen and holding the semiconductor wafer such that the lower surface of the semiconductor wafer is uniformly contacted with the polishing pad. A pressure detecting sensor senses the pressure applied from the semiconductor wafer on the polishing pad and outputs a corresponding signal.

Abstract translation: 一种用于在化学机械抛光装置中调平半导体晶片的改进的感测装置和方法，其容易地检测来自与抛光表面接触的半导体晶片的压力变化。 本发明包括具有在其上平面上的抛光垫并且固定到可旋转的压板驱动轴的抛光台板。 载体可旋转地设置在研磨台板的上表面上并保持半导体晶片，使得半导体晶片的下表面与抛光垫均匀地接触。 压力检测传感器感测从抛光垫上的半导体晶片施加的压力，并输出相应的信号。

公开(公告)号：US20130152038A1

公开(公告)日：2013-06-13

申请号：US13316256

申请日：2011-12-09

Applicant: JongHwa Lim ,  Samuel Chung ,  Yong Jin Kim ,  Soo Youn Cho ,  Duhoi Heo ,  Chang Youl Hong ,  Jun Yong Kim ,  Daniel Broekman ,  Ina Teegan ,  John Thoni

Inventor： JongHwa Lim ,  Samuel Chung ,  Yong Jin Kim ,  Soo Youn Cho ,  Duhoi Heo ,  Chang Youl Hong ,  Jun Yong Kim ,  Daniel Broekman ,  Ina Teegan ,  John Thoni

IPC: G06F9/44

CPC classification number: G06Q10/103

Abstract: A system includes a workflow design application further including a user interface for displaying at least one project server platform type available for selection, and a project mode module configured to retrieve at least one available customizable project workflow component from the project server via a project server application programming interface (API). The user interface is configured to receive a project server platform type selection via the user interface, and, upon receiving the project server platform type selection, display the retrieved at least one customizable project workflow component, receive at least one customizable project workflow component selection, receive a customization selection for the selected customizable project workflow component, and receive a request to generate at least a portion of a project workflow based on the customization selection for the selected customizable project workflow component.

Abstract translation: 一种系统包括工作流设计应用，其进一步包括用于显示可供选择的至少一个项目服务器平台类型的用户界面，以及被配置为经由项目服务器应用从项目服务器检索至少一个可自定义的项目工作流组件的项目模式模块 编程接口（API）。 所述用户界面被配置为经由所述用户界面接收项目服务器平台类型选择，并且在接收到所述项目服务器平台类型选择时，显示所检索的至少一个可定制的项目工作流组件，接收至少一个可定制的项目工作流组件选择， 接收所选择的可定制项目工作流程组件的定制选择，并根据所选择的可定制项目工作流程组件的自定义选择，接收生成项目工作流的至少一部分的请求。