公开(公告)号：US20220102406A1

公开(公告)日：2022-03-31

申请号：US17546740

申请日：2021-12-09

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd. ,  Shanghai Tianma Micro-Electronics Co., Ltd.

Inventor： Kerui XI ,  Xuhui PENG ,  Feng QIN ,  Tingting CUI ,  Zhenyu JIA

IPC: H01L27/146 ,  H01L25/16

Abstract: The present disclosure provides chip package structure, packaging method, camera module and electronic equipment. The package structure includes chip package module, which includes light-transmitting substrate, wiring layer located on side of light-transmitting substrate and including first metal wire, conductor located on side of wiring layer facing away from light-transmitting substrate, photosensitive chip located on side of wiring layer facing away from the light-transmitting substrate, active chip located on side of wiring layer facing away from light-transmitting substrate, and plastic encapsulation layer encapsulating photosensitive chip and active chip. The conductor includes first end electrically connected to first metal wire, and second end. The photosensitive chip includes pin electrically connected to first metal wire and has photosensitive surface facing towards light-transmitting substrate. The photosensitive surface includes photosensitive region that is not overlapping first metal wire. The active chip includes pin electrically connected to first metal wire.

公开(公告)号：US20210322981A1

公开(公告)日：2021-10-21

申请号：US17363792

申请日：2021-06-30

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Xiangjian KONG ,  Jiubin ZHOU ,  Guicai WANG ,  Yajie WANG ,  Tingting CUI

IPC: B01L3/00 ,  G01N27/22 ,  G09G3/34 ,  H01L27/12 ,  H03K17/687 ,  H05B45/30

Abstract: A panel includes a substrate, an array layer and an electrode array layer. The array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer. The substrate includes drive units arranged in an array, scan line groups, data lines extending in a second direction; and common signal lines extending in the second direction. The scan line group includes first scan lines and second scan lines, extending in a first direction. The first direction is perpendicular with the second direction. The electrode array layer includes drive electrodes arranged in an array; the drive electrodes correspond to the drive units; and the drive unit includes a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor.

公开(公告)号：US20200316590A1

公开(公告)日：2020-10-08

申请号：US16455013

申请日：2019-06-27

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Xiangjian KONG ,  Jiubin ZHOU ,  Guicai WANG ,  Yajie WANG ,  Tingting CUI

IPC: B01L3/00 ,  H01L27/12 ,  H03K17/687 ,  G01N27/22 ,  G09G3/34

Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal, which are electrically connected with each other. The step-up unit includes a first module, a second module, a third module and a first capacitor, which are electrically connected with each other. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor. The third module is configured to transmit a signal of the third signal input terminal to the second electrode of the first capacitor, which further increases the signal of the first electrode of the first capacitor.

公开(公告)号：US20200312772A1

公开(公告)日：2020-10-01

申请号：US16441501

申请日：2019-06-14

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Yuan DING

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

公开(公告)号：US20200312763A1

公开(公告)日：2020-10-01

申请号：US16441243

申请日：2019-06-14

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI ,  Xuhui PENG

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L49/02 ,  H01L25/16 ,  H01L21/56

Abstract: Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a first metal layer, a second metal layer, and bare chips. The bare chips include first bare chips and second bare chips. First-connecting-posts are formed on a side of the first bare chips and on a side of the second bare chips. The encapsulating layer covers the bare chips and the first-connecting-posts. The first metal layer is disposed on the side of the first-connecting-posts away from the bare chips and includes first capacitor polar plates and conductive parts. The first capacitor polar plates are electrically connected to the first-connecting-posts on the first bare chips, and the conductive parts are electrically connected to the first-connecting-posts on the second bare chips. The second metal layer is disposed on a side of the first metal layer away from the encapsulating layer and includes second capacitor polar plates electrically connected to the conductive parts.

公开(公告)号：US20220197437A1

公开(公告)日：2022-06-23

申请号：US17197329

申请日：2021-03-10

Applicant: Shanghai AVIC OPTO Electronics Co.,Ltd.

Inventor： Liyan LI ,  Lu YAO ,  Feng QIN

IPC: G06F3/044 ,  G06F3/041 ,  A61L2/10

Abstract: A touch panel and a method for forming a touch panel, a touch module and a touch display panel are provided. The touch panel includes a substrate including a touch area and a bonding area located at one side of the touch area; a plurality of touch electrodes located in the touch area; a plurality of touch leads connected with the plurality of touch electrodes in a one-to-one correspondence and extending to the bonding area; a plurality of ultraviolet light-emitting modules located in the touch area; and a plurality of light-emitting leads electrically connected with the plurality of ultraviolet light-emitting module in a one-to-one correspondence and extending to the bonding area.

公开(公告)号：US20180321782A1

公开(公告)日：2018-11-08

申请号：US16022641

申请日：2018-06-28

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd,

Inventor： Feng QIN ,  Shou Fu JIAN ,  Zhi Qiang XIA ,  Zhao Keng CAO

IPC: G06F3/041 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333 ,  G06F3/047

CPC classification number: G06F3/0412 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/136286 ,  G02F1/1368 ,  G06F3/047

Abstract: The present disclosure provides display panel and display device. The display panel includes: a plurality of sub-pixel units defined by the plurality of data lines intersecting the plurality of scanning lines in an insulation manner. The plurality of sub-pixel units constitutes a plurality of rendering pixel units arranged in an array. Each of the plurality of rendering pixel units includes at least two adjacent sub-pixel units in a row of sub-pixel units, and a number of sub-pixel units included in each of the plurality of rendering pixel units is smaller than a total number of colors corresponding to color resists in the display panel. In each row of sub-pixel units, at least two rendering pixel units of the plurality of rendering pixel units are disposed between two adjacent touch lines. In each column of rendering pixel units, each rendering pixel unit performs color rendering with its adjacent sub-pixel unit.

公开(公告)号：US20220293544A1

公开(公告)日：2022-09-15

申请号：US17829619

申请日：2022-06-01

Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Feng QIN ,  Kerui XI ,  Tingting CUI ,  Jie ZHANG ,  Xuhui PENG

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes the followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes expose one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.

公开(公告)号：US20220137463A1

公开(公告)日：2022-05-05

申请号：US17125535

申请日：2020-12-17

Applicant: Shanghai AVIC OPTO Electronics Co.,Ltd. ,  Tianma Micro-Electronics Co., Ltd.

Inventor： Feng QIN ,  Zhiqi CHEN ,  Dandan QIN ,  Shoufu JIAN

IPC: G02F1/1335 ,  G02F1/13357

Abstract: A light-emitting structure, a backlight module, a display module, and a display device are provided. The light-emitting structure includes a circuit substrate, including a first surface and a second surface sequentially arranged along a light-exiting direction of the light-emitting structure. The circuit substrate also includes a light-transparent substrate and a wiring structure located on a side of the light-transparent substrate in a thickness direction. The light-emitting structure also includes a plurality of light-emitting elements, arranged in an array on one of the first surface or the second surface of the circuit substrate. The plurality of the light-emitting elements is electrically connected to the wiring structure. The light-emitting structure also includes a heat sink, located on a side of the first surface of the circuit substrate. The heat sink is configured for dissipating heat generated by the plurality of the light-emitting elements.

公开(公告)号：US20200306754A1

公开(公告)日：2020-10-01

申请号：US16444282

申请日：2019-06-18

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Kerui XI ,  Feng QIN ,  Jine LIU ,  Xiaohe LI ,  Tingting CUI

IPC: B01L3/00

Abstract: A microfluidic chip, a method for driving a microfluidic chip and an analysis apparatus are provided. An exemplary microfluidic chip includes a substrate; a number of M driving electrodes disposed on a side of the substrate and arranged along a first direction; and a number of N signal terminals electrically connected to the number of M driving electrodes. Any three adjacent driving electrodes are connected to different signal terminals, respectively; a number of A of the number of M driving electrodes are connected to a same signal terminal; and M, N and A are positive integers, and M≥4, N≥3, M>N, and A≥2.