公开(公告)号：US08853697B2

公开(公告)日：2014-10-07

申请号：US13776999

申请日：2013-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd. ,  Sharp Kabushiki Kaisha

Inventor： Kenichi Okazaki ,  Takuya Matsuo ,  Yoshitaka Yamamoto ,  Hiroshi Matsukizono ,  Yosuke Kanzaki

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78603

Abstract: To inhibit a metal element contained in a glass substrate from being diffused into a gate insulating film or an oxide semiconductor film. A semiconductor device includes a glass substrate, a base insulating film formed using metal oxide over the glass substrate, a gate electrode formed over the base insulating film, a gate insulating film formed over the gate electrode, an oxide semiconductor film which is formed over the gate insulating film and overlapping with the gate electrode, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In a region of the base insulating film that is present in a range of 3 nm or less from a surface of the base insulating film, the concentration of a metal element contained in the glass substrate is less than or equal to 1×1018 atoms/cm3.

Abstract translation: 抑制包含在玻璃基板中的金属元素扩散到栅极绝缘膜或氧化物半导体膜中。 半导体器件包括玻璃衬底，在玻璃衬底上形成的使用金属氧化物的基底绝缘膜，形成在基底绝缘膜上的栅极电极，形成在栅电极上的栅极绝缘膜，形成在该绝缘膜上的氧化物半导体膜， 栅极绝缘膜并与栅电极重叠，以及与氧化物半导体膜电连接的源电极和漏电极。 在基极绝缘膜的与基底绝缘膜的表面存在3nm以下的范围的区域中，玻璃基板中所含的金属元素的浓度小于或等于1×1018原子/ cm3。

公开(公告)号：US10269831B2

公开(公告)日：2019-04-23

申请号：US15039118

申请日：2014-08-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Takao Saitoh ,  Seiji Kaneko ,  Yohsuke Kanzaki ,  Yutaka Takamaru ,  Keisuke Ide ,  Takuya Matsuo ,  Shigeyasu Mori ,  Hiroshi Matsukizono

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/786 ,  H01L29/10 ,  H01L29/12

Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.

公开(公告)号：US09520476B2

公开(公告)日：2016-12-13

申请号：US14375912

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Seiichi Uchida ,  Takuya Matsuo

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/441 ,  H01L29/786 ,  H01L29/66 ,  H01L27/32

CPC classification number: H01L29/4908 ,  H01L21/441 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 半导体器件（100A）包括基板（2），形成在基板（2）上的氧化物半导体层（5），与氧化物半导体层（5）电连接的源极和漏极（6s，6d） 电连接到漏电极（6d）的透明电极（7），形成在源极和漏极（6s，6d）上的电介质层（8）和形成在电介质层（8）上的第二透明电极（9） 。 第一透明电极（7）的上表面和/或下表面与还原绝缘层（8a）接触，具有还原包含在氧化物半导体层（5）中的氧化物半导体的性质。 第二透明电极（9）经由电介质层（8）至少部分地与第一透明电极（7）重叠。 氧化物半导体层（5）和第一透明电极（7）由相同的氧化膜形成。

公开(公告)号：US12048199B2

公开(公告)日：2024-07-23

申请号：US17940860

申请日：2022-09-08

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masatomo Honjo ,  Hiroshi Matsukizono ,  Takuya Matsuo

IPC: H01L27/32 ,  H10K59/121 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/7869 ,  H10K59/1201

Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.

公开(公告)号：US11476314B2

公开(公告)日：2022-10-18

申请号：US17040909

申请日：2018-03-29

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masatomo Honjo ,  Hiroshi Matsukizono ,  Takuya Matsuo

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/32 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.

公开(公告)号：US09214533B2

公开(公告)日：2015-12-15

申请号：US14375917

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Takuya Matsuo ,  Seiichi Uchida

IPC: H01L29/66 ,  H01L29/45 ,  H01L27/12 ,  H01L23/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/44 ,  G02F1/1362 ,  G02F1/1343

CPC classification number: H01L29/66969 ,  G02F1/136213 ,  G02F2001/134372 ,  G02F2201/40 ,  G02F2201/50 ,  H01L21/02565 ,  H01L21/44 ,  H01L23/564 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/45 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 该半导体器件（100A）包括：衬底（2）; 形成在所述基板（2）上的栅极（3）; 形成在所述栅电极（3）上方的栅极绝缘层（4）; 形成在栅极绝缘层（4）上的氧化物半导体层（5）; 电连接到氧化物半导体层（5）的源极和漏极（6s，6d）; 电连接到漏极（6d）的第一透明电极（7）; 包括形成在所述源极和漏极（6s，6d）上的电介质层（8a）的层间绝缘层（8）; 和形成在层间绝缘层（8）上的第二透明电极（9）。 第二透明电极（9）的至少一部分与第一透明电极（7）重叠，电介质层（8a）介于它们之间，形成氧化物半导体层（5）和第一透明电极（7） 在相同的氧化膜上。

公开(公告)号：US20150041800A1

公开(公告)日：2015-02-12

申请号：US14375914

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Seiichi Uchida ,  Takuya Matsuo

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2201/40 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693

Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 该半导体器件（100A）包括：衬底（1）; 形成在基板（1）上的栅电极（3）和第一透明电极（2）; 形成在栅电极（3）和第一透明电极（2）上的第一绝缘层（4）; 形成在所述第一绝缘层（4）上的氧化物半导体层（5）; 电连接到氧化物半导体层（5）的源极和漏极（6s，6d）; 和与漏电极（6d）电连接的第二透明电极（7）。 第一透明电极（2）的至少一部分与第二透明电极（7）重叠，第一绝缘层（4）插入其间，氧化物半导体层（5）和第二透明电极（7）为 由相同的氧化膜形成。

公开(公告)号：US20140367677A1

公开(公告)日：2014-12-18

申请号：US14375917

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Takuya Matsuo ,  Seiichi Uchida

IPC: H01L29/66 ,  H01L29/45 ,  H01L27/12 ,  H01L21/02 ,  H01L23/00 ,  H01L29/786 ,  H01L21/44

CPC classification number: H01L29/66969 ,  G02F1/136213 ,  G02F2001/134372 ,  G02F2201/40 ,  G02F2201/50 ,  H01L21/02565 ,  H01L21/44 ,  H01L23/564 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/45 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 该半导体器件（100A）包括：衬底（2）; 形成在所述基板（2）上的栅极（3）; 形成在所述栅电极（3）上方的栅极绝缘层（4）; 形成在栅极绝缘层（4）上的氧化物半导体层（5）; 电连接到氧化物半导体层（5）的源极和漏极（6s，6d）; 电连接到漏极（6d）的第一透明电极（7）; 包括形成在所述源极和漏极（6s，6d）上的电介质层（8a）的层间绝缘层（8）; 和形成在层间绝缘层（8）上的第二透明电极（9）。 第二透明电极（9）的至少一部分与第一透明电极（7）重叠，电介质层（8a）介于它们之间，形成氧化物半导体层（5）和第一透明电极（7） 在相同的氧化膜上。

公开(公告)号：US20140361295A1

公开(公告)日：2014-12-11

申请号：US14375912

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Seiichi Uchida ,  Takuya Matsuo

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/441 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/4908 ,  H01L21/441 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 半导体器件（100A）包括基板（2），形成在基板（2）上的氧化物半导体层（5），与氧化物半导体层（5）电连接的源极和漏极（6s，6d） 电连接到漏电极（6d）的透明电极（7），形成在源极和漏极（6s，6d）上的电介质层（8）和形成在电介质层（8）上的第二透明电极（9） 。 第一透明电极（7）的上表面和/或下表面与还原绝缘层（8a）接触，具有还原包含在氧化物半导体层（5）中的氧化物半导体的性质。 第二透明电极（9）经由电介质层（8）至少部分地与第一透明电极（7）重叠。 氧化物半导体层（5）和第一透明电极（7）由相同的氧化膜形成。

公开(公告)号：US09276126B2

公开(公告)日：2016-03-01

申请号：US14375914

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Seiichi Uchida ,  Takuya Matsuo

IPC: H01L29/12 ,  H01L29/786 ,  G02F1/1368 ,  H01L29/49 ,  H01L27/12 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2201/40 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693

Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 该半导体器件（100A）包括：衬底（1）; 形成在基板（1）上的栅电极（3）和第一透明电极（2）; 形成在栅电极（3）和第一透明电极（2）上的第一绝缘层（4）; 形成在所述第一绝缘层（4）上的氧化物半导体层（5）; 电连接到氧化物半导体层（5）的源极和漏极（6s，6d）; 和与漏电极（6d）电连接的第二透明电极（7）。 第一透明电极（2）的至少一部分与第二透明电极（7）重叠，第一绝缘层（4）插入其间，氧化物半导体层（5）和第二透明电极（7）为 由相同的氧化膜形成。