公开(公告)号：US10388676B2

公开(公告)日：2019-08-20

申请号：US15743369

申请日：2016-08-04

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takao Saitoh ,  Yohsuke Kanzaki ,  Makoto Nakazawa ,  Kazuatsu Ito ,  Seiji Kaneko

IPC: G09G3/36 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1368 ,  G06F3/044 ,  H01L21/768 ,  G02F1/1362 ,  G06F3/041 ,  G02F1/1333

Abstract: An active matrix substrate (1001) includes a connecting portion (101). The connecting portion. (101) includes a lower conductive layer supported by a substrate; a first insulating layer formed so as to cover the lower conductive layer (2) and having a contact hole (6p) that exposes a part of the lower conductive layer (2); a bottom conductive film (4) that is disposed in the contact hole (6p) and covers at least a part of the exposed part of the lower conductive layer (2), the exposed part being exposed by the contact hole (6p); a second insulating layer (9) that is formed on the first insulating layer (6) and in the contact hole (6p), is in contact with the bottom conductive film (4) in the contact hole (6p), and has an opening (9p) that exposes a part of the bottom conductive film (4); and an upper conductive layer (8) that is disposed on the second insulating layer (9) and in the opening (9p) and is in contact with the bottom conductive film (4) in the opening (9p). The entire bottom conductive film (4) is located on the substrate side relative to the upper surface of the first insulating layer (6).

公开(公告)号：US09379250B2

公开(公告)日：2016-06-28

申请号：US14408626

申请日：2013-06-12

Applicant: Sharp Kabushiki Kaisha

Inventor： Seiichi Uchida ,  Yasuyuki Ogawa ,  Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Yutaka Takamaru ,  Makoto Nakazawa ,  Mitsunobu Miyamoto

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/441 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/441 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.

Abstract translation: 该半导体器件（100A）包括：衬底（2）; 形成在所述基板（2）上的栅极（3）; 形成在所述栅电极（3）上方的栅极绝缘层（4）; 形成在栅极绝缘层（4）上的氧化物半导体层（5）; 电连接到氧化物半导体层（5）的源极和漏极（6s，6d）; 电连接到漏极（6d）的第一透明电极（7）; 包括形成在源极和漏极（6s，6d）上的部分的层间绝缘层（8a）; 和形成在层间绝缘层（8a）上的第二透明电极（9）。 第二透明电极（9）的至少一部分与第一透明电极（7）重叠，层间绝缘层（8a）介于它们之间。 并且氧化物半导体层（5）和第一透明电极（7）由相同的氧化膜形成。

公开(公告)号：US09305939B2

公开(公告)日：2016-04-05

申请号：US14406046

申请日：2013-05-28

Applicant: Sharp Kabushiki Kaisha

Inventor： Yutaka Takamaru ,  Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869

Abstract: A semiconductor device has: a first transparent electrode, a drain electrode, and a source electrode formed on a substrate; an oxide layer joined electrically to the source electrode and the drain electrode and containing a semiconductor region; an insulating layer formed on the oxide layer and the first transparent electrode; a gate electrode formed on the insulating layer; and a second transparent electrode formed so as to overlap at least a part of the first transparent electrode with the insulating layer interposed therebetween. The oxide layer and the first transparent electrode are formed of the same oxide film.

Abstract translation: 半导体器件具有：形成在基板上的第一透明电极，漏电极和源电极; 氧化层，其与源电极和漏电极电连接并且包含半导体区域; 形成在所述氧化物层和所述第一透明电极上的绝缘层; 形成在所述绝缘层上的栅电极; 以及第二透明电极，其形成为与所述第一透明电极的至少一部分重叠，并且所述绝缘层位于所述第二透明电极之间。 氧化物层和第一透明电极由相同的氧化膜形成。

公开(公告)号：US09209282B2

公开(公告)日：2015-12-08

申请号：US14373461

申请日：2013-01-16

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuatsu Ito ,  Hidehito Kitakado

IPC: H01L29/786 ,  H01L29/66 ,  H01L23/532 ,  H01L27/12 ,  H01L29/45 ,  H01L21/02 ,  H01L21/441 ,  H01L21/477 ,  H01L29/417 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L29/66969 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/477 ,  H01L23/53238 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention includes at least a step forming a source electrode (32) and a drain electrode (33), each of which is a multilayer film of a first conductive film (32a), (33a) made of titanium or molybdenum, a second conductive film (32b), (33b) made of copper, and a third conductive film (32c), (33c) made of titanium oxide, a step of forming passivation film (18), which is an inorganic insulating film, on an oxide semiconductor layer (13), the source electrode (32) and drain electrode (33), and an annealing step of annealing the oxide semiconductor layer (13).

Abstract translation: 本发明至少包括形成源电极（32）和漏极（33）的步骤，所述源电极（32）和漏电极（33）是由钛或钼制成的第一导电膜（32a），（33a）的多层膜，第二 由铜制成的导电膜（32b），（33b）以及由氧化钛制成的第三导电膜（32c），（33c），在氧化物上形成作为无机绝缘膜的钝化膜（18） 半导体层（13），源电极（32）和漏电极（33）以及退火氧化物半导体层（13）的退火步骤。

公开(公告)号：US20150123117A1

公开(公告)日：2015-05-07

申请号：US14400592

申请日：2013-04-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuatsu Ito ,  Tadayoshi Miyamoto ,  Yasuyuki Ogawa ,  Seiichi Uchida

IPC: H01L29/786 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136231 ,  H01L21/441 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969

Abstract: A TFT substrate (100A) includes an oxide layer (15) which has a semiconductor region (5) and a conductor region (7) and in which the semiconductor region overlaps at least partially with a gate electrode (3a) with a first insulating layer (4) interposed between them, a protective layer (8) which covers the channel region of the semiconductor region, and a transparent electrode (9) which is arranged to overlap with at least a portion of the conductor region when viewed along a normal to the substrate (2). An end portion of the oxide layer is at least partially covered with the protective layer.

Abstract translation: TFT基板（100A）包括具有半导体区域（5）和导体区域（7）的氧化物层（15），其中半导体区域至少部分地与栅电极（3a）重叠，第一绝缘层 （4），覆盖半导体区域的沟道区域的保护层（8）和透明电极（9），该透明电极设置成与沿着导电区域的法线方向观察时的导体区域的至少一部分重叠 基板（2）。 氧化物层的端部至少部分被保护层覆盖。

公开(公告)号：US20150069381A1

公开(公告)日：2015-03-12

申请号：US14389810

申请日：2013-04-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Mitsunobu Miyamoto ,  Yutaka Takamaru

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78606

Abstract: This semiconductor device (100A) includes: a gate electrode (3) formed on a substrate (2); a gate insulating layer (4) formed on the gate electrode; an oxide layer (50) which is formed on the gate insulating layer and which includes a semiconductor region (51) and a conductor region (55); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region; a protective layer (11) formed on the source and drain electrodes; and a transparent electrode (9) formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer (61) with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.

Abstract translation: 该半导体装置（100A）具备：形成在基板（2）上的栅电极（3） 形成在所述栅电极上的栅极绝缘层（4） 形成在所述栅极绝缘层上并且包括半导体区域（51）和导体区域（55）的氧化物层（50）; 电连接到半导体区域的源电极和漏电极（6s，6d） 形成在所述源极和漏极上的保护层（11）; 和形成在保护层上的透明电极（9）。 透明电极的至少一部分与导体区域重叠，保护层插在它们之间。 导体区域的上表面与减少绝缘层（61）接触，具有还原包含在氧化物层中的氧化物半导体的性质。 还原绝缘层与半导体区域的沟道区域不接触。

公开(公告)号：US12058891B2

公开(公告)日：2024-08-06

申请号：US17276423

申请日：2018-09-18

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Kazuatsu Ito

IPC: H10K59/121 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78696 ,  H10K59/1201

Abstract: A display device includes a gate electrode, a gate insulating film, a first metal oxide layer having crystallinity, and a second metal oxide layer having non-crystallinity. The first metal oxide layer and the second metal oxide layer are sequentially laminated on a substrate. The first metal oxide layer and the second metal oxide layer are in contact with each other in all regions where the first metal oxide layer and the second metal oxide layer overlap each other. The first metal oxide layer at least partially has a first semiconductor region serving as a semiconductor. One of the first metal oxide layer and the second metal oxide layer at least partially has a conductor region made electrically conductive.

公开(公告)号：US10663821B2

公开(公告)日：2020-05-26

申请号：US15772062

申请日：2016-11-01

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takao Saitoh ,  Yohsuke Kanzaki ,  Makoto Nakazawa ,  Kazuatsu Ito ,  Seiji Kaneko

IPC: G02F1/1362 ,  G06F3/044 ,  G02F1/1345 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/1333 ,  G06F3/041

Abstract: An array board includes input terminals, a first interlayer insulating film, a first planarization film, terminal lines, a second planarization film, and protective members. A first interlayer insulating film edge section and a first planarization film edge section are disposed between the input terminals and the display area. The terminal lines in a layer upper than the first planarization film and extending to cross the first interlayer insulating film edge section and the first planarization film edge section are connected to the input terminals. The second planarization film in a layer upper than the terminal lines includes a second planarization film edge section disposed closer to the input terminals relative to the first interlayer insulating edge section and the first planarization film edge section. The protective members in a layer upper than the second planarization film cover sections of the terminals lines not overlapping the second planarization film, respectively.

公开(公告)号：US10297694B2

公开(公告)日：2019-05-21

申请号：US15767699

申请日：2016-10-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuatsu Ito

IPC: H01L21/28 ,  H01L27/08 ,  H01L27/32 ,  H01L29/04 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: A semiconductor device includes a first thin film transistor (101) on a substrate (10), the first thin film transistor including: a sub-gate electrode (12); a first insulating layer (14) covering the sub-gate electrode; a main gate electrode (16) formed on the first insulating layer; a second insulating layer (18) covering the main gate electrode; an oxide semiconductor layer (20) having a layered structure of a first layer (20A) and a second layer (20B), the second layer having a larger band gap than the first layer; a first source electrode (22); and a first drain electrode (24), wherein as seen from a direction normal to the substrate, the oxide semiconductor layer (20) includes: a gate opposing region (20g) that overlaps the main gate electrode; a source contact region that is in contact with the first source electrode (22); a drain contact region that is in contact with the first drain electrode; and an offset region (30s, 30d) that is provided at least one of between the gate opposing region and the source contact region and between the gate opposing region and the drain contact region, wherein at least a portion of the offset region overlaps the sub-gate electrode (12) with the first insulating layer (14) and the second insulating layer (18) therebetween.

公开(公告)号：US09520476B2

公开(公告)日：2016-12-13

申请号：US14375912

申请日：2013-01-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tadayoshi Miyamoto ,  Kazuatsu Ito ,  Shigeyasu Mori ,  Mitsunobu Miyamoto ,  Yasuyuki Ogawa ,  Makoto Nakazawa ,  Seiichi Uchida ,  Takuya Matsuo

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/441 ,  H01L29/786 ,  H01L29/66 ,  H01L27/32

CPC classification number: H01L29/4908 ,  H01L21/441 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract translation: 半导体器件（100A）包括基板（2），形成在基板（2）上的氧化物半导体层（5），与氧化物半导体层（5）电连接的源极和漏极（6s，6d） 电连接到漏电极（6d）的透明电极（7），形成在源极和漏极（6s，6d）上的电介质层（8）和形成在电介质层（8）上的第二透明电极（9） 。 第一透明电极（7）的上表面和/或下表面与还原绝缘层（8a）接触，具有还原包含在氧化物半导体层（5）中的氧化物半导体的性质。 第二透明电极（9）经由电介质层（8）至少部分地与第一透明电极（7）重叠。 氧化物半导体层（5）和第一透明电极（7）由相同的氧化膜形成。