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公开(公告)号：US07994009B2
公开(公告)日：2011-08-09
申请号：US12492743
申请日：2009-06-26
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L29/66537 , H01L29/6659 , H01L29/66659
摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.
摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。
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公开(公告)号：US08405154B2
公开(公告)日：2013-03-26
申请号：US13167538
申请日：2011-06-23
IPC分类号： H01L21/70
CPC分类号： H01L21/823437 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L29/66537 , H01L29/6659 , H01L29/66659
摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.
摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。
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公开(公告)号：US20100327374A1
公开(公告)日：2010-12-30
申请号：US12492743
申请日：2009-06-26
IPC分类号： H01L27/088 , H01L21/77 , H01L21/265
CPC分类号： H01L21/823437 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L29/66537 , H01L29/6659 , H01L29/66659
摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.
摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电性质的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。
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公开(公告)号：US08114729B2
公开(公告)日：2012-02-14
申请号：US11870255
申请日：2007-10-10
IPC分类号： H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/28052 , H01L21/32155 , H01L21/823842 , H01L27/0922 , Y10S257/903
摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.
摘要翻译： 一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。 多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。 多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。 然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域 在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。
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公开(公告)号：US20090096031A1
公开(公告)日：2009-04-16
申请号：US11870255
申请日：2007-10-10
IPC分类号： H01L27/11 , H01L21/3205
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/28052 , H01L21/32155 , H01L21/823842 , H01L27/0922 , Y10S257/903
摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.
摘要翻译： 一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。 多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。 多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。 然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域 在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。
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公开(公告)号：US08609483B2
公开(公告)日：2013-12-17
申请号：US12825002
申请日：2010-06-28
申请人： Kamel Benaissa , Greg C. Baldwin
发明人： Kamel Benaissa , Greg C. Baldwin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L27/092
摘要： Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.
摘要翻译： 在隔离的p阱中构造的电气设备结构，其完全包含在核心n阱内。 在使用基准CMOS工艺流程中完全包含在核心n阱内的隔离p-阱内形成电子器件的方法。
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公开(公告)号：US08232158B2
公开(公告)日：2012-07-31
申请号：US12824944
申请日：2010-06-28
申请人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
发明人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
IPC分类号： H01L21/8249
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823878 , H01L27/0922
摘要： An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
摘要翻译： 形成在第一n阱中的核心PMOS晶体管和形成在第二n阱中的隔离DENMOS（iso-DENMOS）晶体管的集成电路，其中第一和第二n-阱的深度和掺杂相同。 形成集成电路的方法，其形成在第一n阱中形成的核心PMOS晶体管晶体管和形成在第二n阱中的等效DONMOS晶体管，其中第一和第二n-阱的深度和掺杂相同。
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公开(公告)号：US20110156144A1
公开(公告)日：2011-06-30
申请号：US12824944
申请日：2010-06-28
申请人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
发明人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823878 , H01L27/0922
摘要： An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
摘要翻译： 形成在第一n阱中的核心PMOS晶体管和形成在第二n阱中的隔离DENMOS（iso-DENMOS）晶体管的集成电路，其中第一和第二n-阱的深度和掺杂相同。 形成集成电路的方法，其形成在第一n阱中形成的核心PMOS晶体管晶体管和形成在第二n阱中的等效DONMOS晶体管，其中第一和第二n-阱的深度和掺杂相同。
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公开(公告)号：US08604543B2
公开(公告)日：2013-12-10
申请号：US13537196
申请日：2012-06-29
申请人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
发明人： Kamel Benaissa , Greg C. Baldwin , Vineet Mishra , Ananth Kamath
IPC分类号： H01L21/70
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823878 , H01L27/0922
摘要： An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.
摘要翻译： 形成在第一n阱中的核心PMOS晶体管和形成在第二n阱中的隔离DENMOS（iso-DENMOS）晶体管的集成电路，其中第一和第二n-阱的深度和掺杂相同。 形成集成电路的方法，其形成在第一n阱中形成的核心PMOS晶体管晶体管和形成在第二n阱中的等效DONMOS晶体管，其中第一和第二n-阱的深度和掺杂相同。
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公开(公告)号：US08940598B2
公开(公告)日：2015-01-27
申请号：US13288700
申请日：2011-11-03
申请人： Greg Charles Baldwin , Kamel Benaissa , Sarah Liu , Song Zhao
发明人： Greg Charles Baldwin , Kamel Benaissa , Sarah Liu , Song Zhao
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L28/22 , G06F17/5072 , G06F17/5081 , H01L21/265 , H01L21/8238 , H01L27/0629 , H02J7/0044 , H02J7/025
摘要： A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.
摘要翻译： 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。
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