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    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
    1.
    发明授权
    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device 失效
    具有受控量的惰性气体离子的衬底，以减少形成PMOS器件的P-LDD区域的硼掺杂物的沟道和/或扩散

    公开(公告)号：US5717238A

    公开(公告)日：1998-02-10

    申请号：US677078

    申请日：1996-07-09

    申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/26506

    摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

    摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

    Integrated circuit with isolation of field oxidation by noble gas implantation
    3.
    发明授权
    Integrated circuit with isolation of field oxidation by noble gas implantation 失效
    通过惰性气体注入隔离场氧化的集成电路

    公开(公告)号：US6093936A

    公开(公告)日：2000-07-25

    申请号：US918577

    申请日：1997-08-19

    申请人： Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

    发明人： Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

    IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L27/06 ,  H01L29/04

    CPC分类号： H01L27/0688 ,  H01L21/26506 ,  H01L21/76213

    摘要： A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles. Also, the amorphous silicon relieves surface layer stresses which may be present from prior processes or because of prior morphological structural elements formed on the silicon substrate. A boron ion bombardment may also be used to further inhibit loss of P-well dopant to the oxidant forming the field oxidation layer and preserving a desired high field threshold voltage and robust field isolation for the integrated circuit.

    摘要翻译： 硅半导体集成电路包括基本上不会侵入集成电路的有源电路元件的绝缘场氧化层。 场氧化层由通过用惰性气体离子轰击硅衬底产生的氧化非晶硅形成。 非晶硅以比结晶硅更快的速度氧化，使得当形成场氧化层时，用于有源电路元件的晶体硅基底基本保持不变。 在惰性气体离子轰击期间，通过使用适当的屏蔽元件形成晶体硅基底。 这种惰性气体离子轰击还具有消除场氧化区域中可能存在的位错缺陷的优点，使得这些缺陷在随后的加热和冷却循环期间不会传播到硅的晶格中。 此外，非晶硅减轻了可能存在于现有工艺中的表面层应力或由于在硅衬底上形成的先前形态结构元件。 还可以使用硼离子轰击来进一步抑制形成场氧化层的氧化剂的P阱掺杂剂的损失，并且为集成电路保留期望的高场阈值电压和鲁棒的场隔离。

    Method of forming source and drain regions for CMOS devices
    5.
    发明授权
    Method of forming source and drain regions for CMOS devices 失效
    形成CMOS器件的源极和漏极区域的方法

    公开(公告)号：US06432759B1

    公开(公告)日：2002-08-13

    申请号：US08259575

    申请日：1994-06-14

    申请人： Yu-Lam Ho

    发明人： Yu-Lam Ho

    IPC分类号： H01L218238

    CPC分类号： H01L21/823814

    摘要： Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped source region, a lightly doped source region, a gate or channel region, a lightly doped drain region, and a moderately doped drain region, arranged consecutively in that order, with the channel region adjacent to the gate having opposite electrical conductivity type to the electrical conductivity type of the source and drain regions. The source region and drain region are formed by ion implantation with ion kinetic energies of 40 keV or more, to increase the width and depth of charge carrier flow in these regions and to thereby reduce the substrate current associated with the device to less than one &mgr;Amp/&mgr;m. Ion implantation of the source and drain regions with ion kinetic energies of 70 keV or more decreases the hot-electron effect and increases the operating lifetime of the device by a multiplicative factor of 20 or more.

    摘要翻译： 用于制造具有降低的衬底电流和增加的器件寿命的NMOS，PMOS或CMOS半导体器件的方法。 源栅极 - 漏极器件被制造成具有中等掺杂源极区，轻掺杂源极区，栅极或沟道区，轻掺杂漏极区和适度掺杂的漏极区，按顺序依次排列，与沟道 与栅极相邻的具有与源极和漏极区域的导电类型相反的导电类型的栅极。 源极区和漏极区通过离子注入形成，其离子动能为40keV或更大，以增加这些区域中载流子流的宽度和深度，从而将与该器件相关的衬底电流减小到小于1μAmp /妈妈 具有70keV或更大的离子动能的离子注入源极和漏极区域降低了热电子效应，并通过乘法因子20或更大而增加了器件的工作寿命。