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    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
    2.
    发明授权
    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device 失效
    具有受控量的惰性气体离子的衬底，以减少形成PMOS器件的P-LDD区域的硼掺杂物的沟道和/或扩散

    公开(公告)号：US5717238A

    公开(公告)日：1998-02-10

    申请号：US677078

    申请日：1996-07-09

    申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/26506

    摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

    摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

    Drive current improvement from recessed SiGe incorporation close to gate
    3.
    发明授权
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US07244654B2

    公开(公告)日：2007-07-17

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    High performance CMOS transistors using PMD liner stress
    4.
    发明授权
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US07192894B2

    公开(公告)日：2007-03-20

    申请号：US10833419

    申请日：2004-04-28

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L21/31

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    Selective area halogen doping to achieve dual gate oxide thickness on a wafer
    5.
    发明授权
    Selective area halogen doping to achieve dual gate oxide thickness on a wafer 失效
    选择性区域卤素掺杂以在晶片上实现双栅极氧化物厚度

    公开(公告)号：US6093659A

    公开(公告)日：2000-07-25

    申请号：US47713

    申请日：1998-03-25

    申请人： Douglas T. Grider ,  Vincent M. McNeil

    发明人： Douglas T. Grider ,  Vincent M. McNeil

    IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L21/37 ,  H01L21/469

    CPC分类号： H01L21/823462 ,  H01L21/26506

    摘要： A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then implanted with a halogen species such as fluorine or chlorine, to retard oxidation. The pattern (36) is then removed and an oxidation step is performed. Oxidation is selectively retarded in areas (14) previously doped with the halogen species but not in the remaining areas (12). Thus, a single oxidation step may be used to form gate oxides (20,22) of different thicknesses.

    摘要翻译： 本文公开了一种用于形成具有多个栅极氧化物厚度的集成电路的方法。 电路（10）被加工成栅极氧化物形成。 然后形成图案（36），暴露需要更薄栅极氧化物（20）的电路的区域。 然后用卤素物质如氟或氯注入这些区域以延缓氧化。 然后去除图案（36），并进行氧化步骤。 在先前掺杂卤素物质的区域（14）中选择性地延迟氧化，但在其余区域（12）中不会氧化。 因此，可以使用单个氧化步骤来形成不同厚度的栅极氧化物（20,22）。

    Nitrogen based implants for defect reduction in strained silicon
    6.
    发明授权
    Nitrogen based implants for defect reduction in strained silicon 有权
    用于应变硅缺陷还原的氮基植入物

    公开(公告)号：US07670892B2

    公开(公告)日：2010-03-02

    申请号：US11268040

    申请日：2005-11-07

    申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

    发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

    摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

    Disposable spacer technology for reduced cost CMOS processing
    7.
    发明授权
    Disposable spacer technology for reduced cost CMOS processing 有权
    一次性间隔技术，可降低CMOS加工成本

    公开(公告)号：US06632718B1

    公开(公告)日：2003-10-14

    申请号：US09339444

    申请日：1999-06-24

    申请人： Douglas T. Grider ,  Terence Breedijk

    发明人： Douglas T. Grider ,  Terence Breedijk

    IPC分类号： H01L21336

    CPC分类号： H01L21/823864

    摘要： A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).

    摘要翻译： 用于源极/漏极注入的制造使用硅锗一次性间隔物（ 114 ）的CMOS晶体管的方法。 在栅极蚀刻之后，形成硅锗一次性间隔物（ 114 ）。 形成暴露NMOS区域（ 120 ）的NMOS抗蚀剂图案（ 116 ）和n型源极/漏极 进行植入。 去除NMOS区域中的一次性间隔物（ 114 ）仍然存在于NMOS抗蚀剂掩模（ 116 ） 位置，执行LDD / MDD植入。 然后可以对PMOS区域重复该过程（ 122 ）。

    Gate fabrication processes for split-gate transistors
    8.
    发明授权
    Gate fabrication processes for split-gate transistors 失效
    分闸晶体管的栅极制造工艺

    公开(公告)号：US06063670A

    公开(公告)日：2000-05-16

    申请号：US60919

    申请日：1998-04-15

    申请人： Bo-Yang Lin ,  Douglas T. Grider ,  George Misium

    发明人： Bo-Yang Lin ,  Douglas T. Grider ,  George Misium

    IPC分类号： H01L21/8234 ,  H01L21/8242

    CPC分类号： H01L21/823462 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/911

    摘要： A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The disposable layer (22) comprises a material that may be removed selectively with respect to silicon and the gate dielectric, such as germanium. If desired, a second dielectric layer (24) may be formed over the disposable layer (22). A pattern (26) is then formed exposing areas (14) of the circuit where a thinner gate dielectric is desired. The second dielectric layer (24), if it is present, and the disposable layer (22) are removed from the exposed areas. The pattern (26) is then removed. Following pre-gate cleaning, the second gate dielectric (30) is formed. The remaining portions of the disposable layer (22) may be removed either prior to, during, or after the second gate dielectric formation (30).

    摘要翻译： 本文公开了一种用于形成具有多个栅极氧化物厚度的集成电路的方法。 电路（10）被加工成栅极氧化物形成。 形成第一栅极电介质（20）。 接下来，在第一栅极电介质（20）上形成一次性层（22）。 一次性层（22）包括可相对于硅和栅极电介质（例如锗）选择性去除的材料。 如果需要，可以在一次性层（22）上形成第二介电层（24）。 然后形成图案（26），暴露需要较薄栅极电介质的电路的区域（14）。 如果存在第二电介质层（24），并且一次性层（22）从暴露区域移除。 然后移除图案（26）。 在栅极清洗之后，形成第二栅极电介质（30）。 一次性层（22）的剩余部分可以在第二栅极电介质形成（30）之前，之中或之后被去除。

    PMD liner nitride films and fabrication methods for improved NMOS performance
    9.
    发明授权
    PMD liner nitride films and fabrication methods for improved NMOS performance 有权
    PMD衬垫氮化物膜和用于改善NMOS性能的制造方法

    公开(公告)号：US08084787B2

    公开(公告)日：2011-12-27

    申请号：US11740426

    申请日：2007-04-26

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L27/118

    CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  Y10S438/938

    摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

    摘要翻译： 提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130），以在NMOS晶体管的一部分或一部分中施加拉伸应力以改善载流子迁移率。 氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。 随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。