公开(公告)号：US5538907A

公开(公告)日：1996-07-23

申请号：US241358

申请日：1994-05-11

申请人： Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

发明人： Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L27/092 ,  H01L21/265

CPC分类号： H01L27/0255 ,  H01L27/0251 ,  H01L27/0259 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0716 ,  H01L27/092

摘要： A CMOS integrate circuit has improved protection to damage from electrostatic discharge (ESD) events because the circuit is formed with a virtual lateral bipolar transistor submerged in the morphology of the integrated circuit beneath an active circuit element of the circuit, and being formed by impurity atoms implanted into the substrate structure as ions which disperse laterally to form a dispersed charge permeation zone through which surge current from an ESD is conducted safely at a current level sufficiently low that the substrate material of the integrated circuit is not damaged. The integrated circuit may be formed with an intrinsic zener diode having a reverse bias breakdown voltage high enough to not interfere with the normal operation of the integrated circuit, and low enough to allow surge current from an ESD event to safely flow to ground potential.

摘要翻译： CMOS集成电路已经改善了对静电放电（ESD）事件的损害的保护，因为电路形成有浸没在电路的有源电路元件下面的集成电路形态的虚拟横向双极晶体管，并由杂质原子 以横向分散形成分散的电荷渗透区域的离子注入到衬底结构中，通过该区域，来自ESD的浪涌电流以足够低的电流水平安全地传导，使得集成电路的衬底材料不被损坏。 该集成电路可以由具有足够高的反偏压击穿电压的本征齐纳二极管形成，以不干扰集成电路的正常工作，并且足够低以允许来自ESD事件的浪涌电流安全地流向地电势。

公开(公告)号：US5358886A

公开(公告)日：1994-10-25

申请号：US86487

申请日：1993-07-01

申请人： Abraham Yee ,  Stanley Yeh ,  Tim Carmichael ,  Gobi Padmanabhan

发明人： Abraham Yee ,  Stanley Yeh ,  Tim Carmichael ,  Gobi Padmanabhan

IPC分类号： H01L29/41 ,  H01L21/768 ,  H01L21/82 ,  H01L27/118 ,  H01L21/265

CPC分类号： H01L21/76886

摘要： An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure. By forming such busses during the initial patterning step to form a genetic structure, and then providing a second patterning step, wherein custom interconnections are formed in the layer of conductive material between electrodes of various active devices, some of the custom interconnections to form specific electrical circuits, formerly implemented at the metal layer level, can be eliminated, thereby reducing the total number of contacts formed between the electrodes and the metal layer or layers, as well as simplifying the metal wiring needed to form the desired electrical circuit.

摘要翻译： 公开了一种集成电路结构及其制造方法，其中导电材料（例如多晶硅）的一个或多个可成形总线将相同导电材料的电极条（例如栅电极条）互连在有源区（例如MOS 岛屿）。 在图案化导电材料层以暴露有源区域并在其上形成电极的初始步骤中，在其上的场氧化物部分上的结构上形成总线。 在进一步处理以在有源区（例如，N-MOS和P-MOS岛中的源极和漏极区）中形成其它电极区之后，但在其上形成金属层的结构之上形成绝缘层之前， 对总线进行进一步的图案化步骤，以根据需要在集成电路结构中的各种电极之间形成定制互连。 通过在初始构图步骤期间形成这样的总线以形成遗传结构，然后提供第二图案化步骤，其中定制互连形成在各种有源器件的电极之间的导电材料层中，一些定制互连形成特定的电 可以消除以前在金属层级实施的电路，从而减少形成在电极和金属层之间的触点的总数，以及简化形成所需电路所需的金属布线。

公开(公告)号：US5796130A

公开(公告)日：1998-08-18

申请号：US578745

申请日：1995-12-26

申请人： Tim Carmichael ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

发明人： Tim Carmichael ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/11807

摘要： A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses. The busses are formed on the gate array structure over field oxide portions thereof during an initial step of patterning the layer of conductive material to expose active areas of differing conductivity type and to form the electrodes thereover. After further processing to form other electrode regions in the active areas such as source and drain regions, but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections between various electrodes in the gate array structure so as to form a desired custom chip.

公开(公告)号：US5593918A

公开(公告)日：1997-01-14

申请号：US233607

申请日：1994-04-22

申请人： Michael D. Rostoker ,  Mark Schneider ,  Nicholas F. Pasch ,  Abraham Yee ,  William C. Schneider

发明人： Michael D. Rostoker ,  Mark Schneider ,  Nicholas F. Pasch ,  Abraham Yee ,  William C. Schneider

IPC分类号： H01L21/768 ,  H01L23/495 ,  H01L23/532 ,  H01L27/02 ,  H01L21/44

CPC分类号： H01L21/76891 ,  H01L23/49579 ,  H01L23/53285 ,  H01L27/0251 ,  H01L2924/0002 ,  Y10S148/09 ,  Y10S148/093 ,  Y10S505/703 ,  Y10S505/706 ,  Y10S505/847 ,  Y10S505/90 ,  Y10T29/49121

摘要： Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g., transistor structures) from over-current or overheating conditions such as those caused by CMOS latch-up. Current density limits and/or thermal limits of superconductors are employed to cause a superconductive trace to become non-superconductive when these limits are exceeded.

摘要翻译： 描述了用于形成超导线的各种技术，其中超导线可以通过冲压，蚀刻，抛光或通过使超导膜（层）非超导的选定区域形成。 超导材料在形成线（迹线）后可以“完善”（或优化）。 在一个实施例中，在衬底中蚀刻沟槽，沟槽用超导材料填充，并且例如通过抛光，去除超过沟槽的任何过量的超导材料。 在另一个实施例中，超导线通过使超导层的选定区域（即，不期望的超导线路以外的区域）通过激光束加热“超导”超导材料或通过离子注入来形成，而不是超导的。 根据本发明形成的超导线可用于保护半导体器件（例如，晶体管结构）免受过度电流或过热条件的影响，例如由CMOS闩锁引起的条件。 采用超导体的电流密度限制和/或热限制，当超过这些限值时，会使超导轨迹变得非超导。

公开(公告)号：US5874754A

公开(公告)日：1999-02-23

申请号：US415173

申请日：1995-03-31

申请人： Jasopin Lee ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

发明人： Jasopin Lee ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/11807

摘要： A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C

摘要翻译： 微电子单元包括半导体衬底，形成在衬底中的有源区，形成在有源区中的栅极和形成在有源区中的第一接触。 接触件具有垂直于有源区域中限定的参考轴线的宽度D，并且与基准轴线间隔最小间隔E.门包括基本上平行于参考轴线延伸的第一部分，第一接触件被布置 在所述第一部分和所述参考轴线之间，所述第一部分与所述第一接触件间隔最小间隔A; 第二部分，其基本上平行于所述参考轴线并且与所述参考轴线间隔开最小间隔C 1（A + D + E），所述第二部分沿着所述参考轴线与所述第一部分间隔开; 以及第三部分，其以与参考轴线成一定角度延伸并且连接在第一和第二部分的相邻端部。 单元的非矩形配置具有压缩的最小间隔，以提供空间节省，与常规门阵列芯片相比，允许在单个芯片上存在更多数量的器件。 在图案化导电材料层以暴露不同导电类型的有源区域并在其上形成电极的初始步骤期间，在其栅极阵列结构上的栅极阵列结构上形成导电材料的一个或多个可模式的总线。 在进一步处理以在诸如源极和漏极区域的有源区域中形成其它电极区域之后，但是在用于在其上形成金属层的结构之上形成绝缘层之前，对总线进行进一步的图案化步骤以形成定制 在门阵列结构中的各种电极之间的互连，以便形成期望的定制芯片。

公开(公告)号：US5723896A

公开(公告)日：1998-03-03

申请号：US771372

申请日：1996-12-16

申请人： Abraham Yee ,  Sheldon Aronowitz

发明人： Abraham Yee ,  Sheldon Aronowitz

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L29/00 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/26533 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/76283

摘要： An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2. When krypton is implanted, the minimum dosage should be at least about 6.times.10.sup.14 krypton atoms/cm.sup.2. The energy used for the implant should be sufficient to provide an average implant depth sufficient to form, after annealing, the noble gas isolation layer at a depth of at least about 0.5 microns from the surface.

摘要翻译： 通过首先用足够量的惰性气体原子注入衬底以抑制随后的半导体晶格的再结晶，在诸如硅半导体晶片的单晶半导体衬底中/之上形成与下面的衬底电垂直隔离的集成电路结构 在随后退火期间的注入区域中，导致形成隔离层，该隔离层包含与衬底中具有充分电阻率充当隔离层的半导体原子嵌入的惰性气体原子。 用于形成这种隔离层的优选稀有气体是氖，氩，氪和氙。 当植入氖原子时，最小剂量应为至少约6×10 15氖原子/ cm 2以抑制随后的硅衬底的再结晶。 当注入氩原子时，最小剂量应至少为约2×1015氩原子/ cm2。 当植入氪时，最小剂量应为至少约6×10 14氪原子/ cm 2。 用于植入物的能量应足以提供足够的平均植入深度，以在退火之后形成距离表面至少约0.5微米深度的惰性气体隔离层。

公开(公告)号：US5721151A

公开(公告)日：1998-02-24

申请号：US484849

申请日：1995-06-07

申请人： Gobi Padmanabhan ,  Abraham Yee

发明人： Gobi Padmanabhan ,  Abraham Yee

IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L21/70

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： A plurality of macro-arrays are formed on a semiconductor substrate. Each macro-array includes a logic area in which a plurality of interconnectable logic gates are formed, and an Input/Output (I/O) area in which a plurality of I/O devices are formed. I/O terminals are formed outside the I/O area, which enable the logic devices of the macro-arrays to be interconnected with the logic devices of the other macro-arrays via the I/O devices. Alternatively, connections can be made directly to the logic devices. The interconnections are made using a pattern of conductors such that the macro-arrays are linked to form a composite gate array which provides a programmed logical functionality. A number of contiguous macro-arrays which provide the required number of gates are used, with the unused macro-arrays being cut away and discarded. The array is mounted on and electrically interconnected with a printed circuit board or other support member using a flip-chip arrangement which provides access to internal I/O connections.

摘要翻译： 在半导体衬底上形成多个宏阵列。 每个宏阵列包括其中形成多个可互连逻辑门的逻辑区域和其中形成有多个I / O设备的输入/输出（I / O）区域。 I / O端子形成在I / O区域之外，这使得宏阵列的逻辑器件能够经由I / O设备与其他宏阵列的逻辑器件互连。 或者，可以直接连接到逻辑设备。 使用导体图案制造互连，使得宏阵列被链接以形成提供编程的逻辑功能的复合门阵列。 使用提供所需数量的门的多个连续的宏阵列，其中未使用的宏阵列被切除并被丢弃。 使用提供对内部I / O连接的访问​​的倒装芯片布置来将阵列安装在印刷电路板或其他支撑构件上并与之电互连。

公开(公告)号：US5648290A

公开(公告)日：1997-07-15

申请号：US366786

申请日：1994-12-30

申请人： Abraham Yee

发明人： Abraham Yee

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L27/105

摘要： A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of annular multi-plate capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.

摘要翻译： CMOS技术DRAM集成电路在衬底中包括成对的P型和N型阱，这些阱使用自对准方法制造。 类似地，使用自对准方法在DRAM的衬底中制造DRAM电路的FET，以在DRAM中提供具有相反极性的FET，其可以具有成对的存储器单元和用于电路对称的虚拟单元。 DRAM包括形成在衬底的FET顶部的多个环形多板电容器结构，以及具有嵌入式位和字迹的多层绝缘电介质，用于将DRAM的多个存储单元连接到外部电路。

公开(公告)号：US5644143A

公开(公告)日：1997-07-01

申请号：US454542

申请日：1995-05-30

申请人： Michael D. Rostoker ,  Mark Schneider ,  Nicholas F. Pasch ,  Abraham Yee ,  William C. Schneider

发明人： Michael D. Rostoker ,  Mark Schneider ,  Nicholas F. Pasch ,  Abraham Yee ,  William C. Schneider

IPC分类号： H01L21/768 ,  H01L23/495 ,  H01L23/532 ,  H01L27/02 ,  H01L29/06 ,  H01L39/00

CPC分类号： H01L21/76891 ,  H01L23/49579 ,  H01L23/53285 ,  H01L27/0251 ,  H01L2924/0002 ,  Y10S148/09 ,  Y10S148/093 ,  Y10S505/703 ,  Y10S505/706 ,  Y10S505/847 ,  Y10S505/90 ,  Y10T29/49121

摘要： Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g., transistor structures) from over-current or overheating conditions such as those caused by CMOS latch-up. Current density limits and/or thermal limits of superconductors are employed to cause a superconductive trace to become non-superconductive when these limits are exceeded.

摘要翻译： 描述了用于形成超导线的各种技术，其中超导线可以通过冲压，蚀刻，抛光或通过使超导膜（层）非超导的选定区域形成。 超导材料在形成线（迹线）后可以“完善”（或优化）。 在一个实施例中，在衬底中蚀刻沟槽，沟槽用超导材料填充，并且例如通过抛光，去除超过沟槽的任何过量的超导材料。 在另一个实施例中，超导线通过使超导层的选定区域（即，不期望的超导线路以外的区域）通过激光束加热“超导”超导材料或通过离子注入来形成，而不是超导的。 根据本发明形成的超导线可用于保护半导体器件（例如，晶体管结构）免受过度电流或过热条件的影响，例如由CMOS闩锁引起的条件。 采用超导体的电流密度限制和/或热限制，当超过这些限值时，会使超导轨迹变得非超导。

公开(公告)号：US5440154A

公开(公告)日：1995-08-08

申请号：US86217

申请日：1993-07-01

申请人： Tim Carmichael ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

发明人： Tim Carmichael ,  Gobi Padmanabhan ,  Abraham Yee ,  Stanley Yeh

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/11807

摘要： A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses. The busses are formed on the gate array structure over field oxide portions thereof during an initial step of patterning the layer of conductive material to expose active areas of differing conductivity type and to form the electrodes thereover. After further processing to form other electrode regions in the active areas such as source and drain regions, but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections between various electrodes in the gate array structure so as to form a desired custom chip.

摘要翻译： 在具有大量通常为MOS器件的部分通用门阵列型芯片中采用的用于MOS器件的新颖配置。 MOS器件具有非矩形构造，并且包括至少一个导电类型的不同于栅极阵列衬底的导电类型的第一和第二区域，该导电类型由形成电极条（例如栅极）的沟道分开。 与常规门阵列芯片相比，MOS器件的非矩形配置提供了空间节省，允许在单个芯片上存在更多数量的器件。 根据本发明的另一方面，由诸如多晶硅的导电材料的一个或多个可模式的总线，诸如门条的MOS器件的互连电极条，其由与母线相同的导电材料制成。 在图案化导电材料层以暴露不同导电类型的有源区域并在其上形成电极的初始步骤中，在其栅极阵列结构上形成总线。 在进一步处理以在诸如源极和漏极区域的有源区域中形成其它电极区域之后，但是在用于在其上形成金属层的结构之上形成绝缘层之前，对总线进行进一步的图案化步骤以形成定制 在门阵列结构中的各种电极之间的互连，以便形成期望的定制芯片。