公开(公告)号：US09999134B2

公开(公告)日：2018-06-12

申请号：US15081623

申请日：2016-03-25

申请人： Multek Technologies Limited

发明人： Mark Zhang ,  Kwan Pen ,  Pui Yin Yu

IPC分类号： H05K1/03 ,  H05K3/04 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00

CPC分类号： H05K3/048 ,  H05K1/036 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09109 ,  H05K2201/0989 ,  H05K2203/0228 ,  H05K2203/1383

摘要： A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.

公开(公告)号：US20170352960A1

公开(公告)日：2017-12-07

申请号：US15149151

申请日：2016-05-08

申请人： Ce Zhang

发明人： Ce Zhang

IPC分类号： H01Q9/04 ,  H01Q21/06 ,  H01Q9/06 ,  H01Q3/26 ,  G02F1/1335

CPC分类号： H01Q9/0464 ,  G02F2001/133541 ,  H01Q1/288 ,  H01Q3/2682 ,  H01Q9/0492 ,  H01Q9/065 ,  H01Q21/06 ,  H01Q21/065 ,  H05K1/0221 ,  H05K1/165 ,  H05K2201/09109 ,  H05K2201/09563 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/10098

摘要： A planar multi-layer assembly method fabricates a dual frequency, dual polarization phased-array antenna. A plurality of vias make up an array of double-walled wells which are connected to a ground plane. A shorted annular ring patch antenna (SARPA) is deposited at the top of each double-walled well. Fabricated coaxially and parallel to each SARPA, is an array of circular patch antennas (CPA). The inner wall of each double-walled well improves isolation of the CPA signals from the SARPA signals. Each SARPA of the array is connected to a pair of first frequency band signal vias and the CPA is coupled to a pair of second frequency band signal vias. Within each frequency band, a plurality of signal phases enable steerable polarized antenna beams.

公开(公告)号：US20170303401A1

公开(公告)日：2017-10-19

申请号：US15609047

申请日：2017-05-31

申请人： HSIO Technologies, LLC

发明人： James J. Rathburn

IPC分类号： H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K3/10 ,  H05K1/16

CPC分类号： H05K1/181 ,  B33Y80/00 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0221 ,  H05K1/0256 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/118 ,  H05K1/16 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/246 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/0367 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155

摘要： A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

公开(公告)号：US20170265298A1

公开(公告)日：2017-09-14

申请号：US15081623

申请日：2016-03-25

申请人： Multek Technologies Limited

发明人： Mark Zhang ,  Kwan Pen ,  Pui Yin Yu

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/06 ,  H05K3/42 ,  H05K1/03 ,  H05K3/46

CPC分类号： H05K3/048 ,  H05K1/036 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/09109 ,  H05K2201/0989 ,  H05K2203/0228 ,  H05K2203/1383

摘要： A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.

公开(公告)号：US20120055702A1

公开(公告)日：2012-03-08

申请号：US13320285

申请日：2010-05-27

申请人： James Rathburn

发明人： James Rathburn

IPC分类号： H05K1/02 ,  H05K3/10

CPC分类号： H05K1/181 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0221 ,  H05K1/0256 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/118 ,  H05K1/16 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/246 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/0367 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155

摘要： A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.

摘要翻译： 包括柔性聚合物膜和柔性聚合物膜的柔性印刷柔性电路以及与聚合物膜结合的至少一个介电层，其具有对应于目标电路几何形状的凹部。 在至少一部分凹部中印刷导电材料以形成电路几何形状。 至少一个电介质覆盖层至少印刷在电路几何形状上。 开口可以印刷在电介质覆盖层中以提供对电路几何形状的至少一部分的访问。

公开(公告)号：US20110143625A1

公开(公告)日：2011-06-16

申请号：US13033307

申请日：2011-02-23

申请人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

发明人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC分类号： H01J9/00

CPC分类号： H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

摘要翻译： 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US07915727B2

公开(公告)日：2011-03-29

申请号：US12385731

申请日：2009-04-17

申请人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

发明人： Kyoung-sei Choi ,  Byung-seo Kim ,  Young-jae Joo ,  Ye-chung Chung ,  Kyong-soon Cho ,  Sang-heui Lee ,  Si-hoon Lee ,  Sa-yoon Kang ,  Dae-woo Son ,  Sang-gui Jo ,  Jeong-kyu Ha ,  Young-sang Cho

IPC分类号： H01L23/498 ,  H01L23/36

CPC分类号： H01L23/49838 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/189 ,  H05K2201/09109 ,  H05K2201/1028 ,  H05K2201/10674 ,  H05K2203/1581 ,  H01L2924/00

摘要： Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

摘要翻译： 公开了一种片上胶片（COF）型半导体封装以及使用其的器件。 COF型半导体封装可以包括包括顶表面和底表面的绝缘衬底，绝缘衬底的顶表面上的半导体器件，绝缘衬底的底表面上的散热部件，以及绝缘衬底的至少一个空间 绝缘基板的底表面和散热部件的顶表面。

公开(公告)号：US20100282497A1

公开(公告)日：2010-11-11

申请号：US12812600

申请日：2008-02-07

申请人： Hiroaki Hashido ,  Masatosi Mitomi

发明人： Hiroaki Hashido ,  Masatosi Mitomi

IPC分类号： H05K1/00

CPC分类号： H05K3/0058 ,  H05K1/0393 ,  H05K3/386 ,  H05K2201/09109 ,  H05K2203/0264 ,  H05K2203/0271

摘要： Release papers (2A, 2B) are bonded to one face of a circuit board (1) via adhesive layers (3A, 3B), so as to cover the adhesive layers. The circuit board (1) is formed of a flexible multilayer board.A nonadhesive portion (4) having no adhesive layers is formed on the portion of the circuit board face located between the adjacent release papers (2A, 2B), and pull-tabs (2Ap, 2Bp) for removing the respective release papers are formed at the end portions of the respective release papers (2A, 2B) located at the nonadhesive portion (4).The pull-tabs are designed so as to face each other preferably at the adhesive portion (4), and the top end portions of the pull-tabs overlap with each other on the circuit board face. With this arrangement, it is possible to recognize the order of removing the respective release papers from the circuit board face.

摘要翻译： 剥离纸（2A，2B）经由粘合剂层（3A，3B）与电路板（1）的一个面接合，以覆盖粘合剂层。 电路板（1）由柔性多层板形成。 在位于相邻的剥离纸（2A，2B）之间的电路板面的部分上形成没有粘合剂层的非粘附部分（4），并且用于去除各剥离纸的拉片（2Ap，2Bp）形成在 位于非粘附部分（4）处的各离型纸（2A，2B）的端部。 拉片被设计为优选地在粘合部分（4）处彼此面对，并且拉片的顶端部分在电路板面上彼此重叠。 通过这种布置，可以从电路板面识别除去各剥离纸的顺序。

公开(公告)号：US07796399B2

公开(公告)日：2010-09-14

申请号：US12317892

申请日：2008-12-30

申请人： James E. Clayton ,  Zakaryae Fathi

发明人： James E. Clayton ,  Zakaryae Fathi

IPC分类号： H05K1/18 ,  H05K7/20 ,  H01R12/24 ,  H01R43/02 ,  H04L12/50 ,  H01L23/34

CPC分类号： H05K1/189 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/07811 ,  H01L2924/15311 ,  H05K1/147 ,  H05K3/0061 ,  H05K2201/043 ,  H05K2201/056 ,  H05K2201/09109 ,  H05K2201/10159 ,  H05K2201/1056 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49179 ,  H01L2924/00

摘要： A multichip module comprises a multilayer substrate circuit having conductive patterns on its surface(s) to which microelectronic device(s) are attached. The conductive patterns include a series of electrical contacts adjacent to one edge of the substrate. The substrate is bonded to two rigid frames, one on each opposite surface. Each substrate has a series of castellations on one edge that are aligned and electrically connected to the respective contacts on the substrate, preferably by soldering. The castellations can serve as a self-aligning mechanism when the module is brought into contact with a low-profile pin array, and the module may be held in place on a motherboard by guide rails in a socket that engages the edges perpendicular to the castellated edge of the module. The module may further be provided with protective heat spreading covers.

摘要翻译： 多芯片模块包括在其表面上具有导电图案的多层衬底电路，微电子器件附接到多个衬底电路。 导电图案包括与衬底的一个边缘相邻的一系列电接触。 衬底被粘合到两个刚性框架上，每个相对表面上一个。 每个衬底在一个边缘上具有一系列在优选通过焊接的衬底上对准并电连接到衬底上的相应接触件的蓖耳。 当模块与低轮廓的针阵列接触时，这些哨座可以用作自对准机构，并且模块可以通过插座中的导轨固定在主板上的位置，该插座与垂直于雉鸡的边缘接合 模块的边缘。 模块还可以设置有保护性散热罩。

公开(公告)号：US07724530B2

公开(公告)日：2010-05-25

申请号：US12317890

申请日：2008-12-30

申请人： James E. Clayton ,  Zakaryae Fathi

发明人： James E. Clayton ,  Zakaryae Fathi

IPC分类号： H05K1/00 ,  H05K7/20

CPC分类号： H05K1/189 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/07811 ,  H01L2924/15311 ,  H05K1/147 ,  H05K3/0061 ,  H05K2201/043 ,  H05K2201/056 ,  H05K2201/09109 ,  H05K2201/10159 ,  H05K2201/1056 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49179 ,  H01L2924/00

摘要： A multichip module comprises a multilayer substrate circuit having conductive patterns on its surface(s) to which microelectronic device(s) are attached. A part of the substrate is flexible and bifurcated. Two rigid members are attached lengthwise, one on either side of the substrate, and the free ends of the bifurcation are reflexed respectively about these members and bonded to them. Electrodes are located on the bifurcations so that they will be exposed outwardly and/or downwardly after reflexing. The module may further be provided with protective heat spreading covers. The electrodes and rigid members may be configured to engage a mating socket or they may be solderable to a printed circuit board.

摘要翻译： 多芯片模块包括在其表面上具有导电图案的多层衬底电路，微电子器件附接到多个衬底电路。 基板的一部分是柔性的并且分叉。 两个刚性构件纵向连接，一个位于衬底的两侧，并且分叉的自由端分别围绕这些构件反射并结合到它们上。 电极位于分叉处，使得它们在反射之后将向外和/或向下暴露。 模块还可以设置有保护性散热罩。 电极和刚性构件可以被配置为接合配合插座，或者它们可焊接到印刷电路板。